灿芯半导体（上海）有限公司

jessie1

ASIC DFT Design Engineer

Job Description:  

1.Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design

2.Generating, simulation  debugging the test patterns for ATE manufacture testing

3. Interface with back-end physical design team to complete timing closure for test related logic

4. Interface with operation team to debug production test-vectors for wafer test  final test

Job Requirements:   

1. BS or MS, major in EE or related discipline

2. Strong experience in ASIC logic design  verification

3. 1+ years work experience in ASIC DFT design

4. Logical thinking  sensitive to the problem with good self-study  problem shooting ability

5. Good communication capability  teamwork spirit

jobic_cn@126.com


Senior Digital Design Engineer

Job Descriptions:

1. Front end design of high speed PHY digital part  

2. Architecture design of high speed PHY digital part

3. RTL implementation  simulation of high speed PHY digital part


Job Qualification

1. M.S. in Electrical engineering or equivalent is required

2. 2 or more years of digital circuit design experience

3. Experience of RTL implementation  mixed signal simulation is required

4. Experience of FPGA verification  using Lab equipment to do testing is preferred

5. Experience of high speed interface PHY design is preferred

6. Understing of analog circuit design is preferred
jobic_cn@126.com


Senior Analog/Mixed Signal Design Engineer
Senior Analog/Mixed Signal Design Engineer

Job Descriptions:
1. High speed interface circuit design (DDR, USB, SATA, etc.)  fundamental components ((a) PLL, DLL, ring/RC OSC, POR (b) SAR/pipeline/sigma-delta ADC, DAC (c) REG, LDO, LVD)
2. Be responsible for the schematic design  simulation
3. Instruct the layout designer to design the circuit layout

Job Qualification
1. M.S. in Electrical engineering or equivalent is required
2. 2 or more years of analog circuit design experience
3. Experience of Spice simulation  mixed-signal simulation.
4. Strong physical layout knowledge  parasitic component understing essential
5. Experience of high speed interface & fundamental circuit design is preferred
6. Process  device physics knowledge is preferred.
jobic_cn@126.com

Senior FPGA Verification Engineer
Job Responsibilities

1. Port whole chip to Altera Stratix4 FPGA development board

2. Anticipate the HW/SW co-simulation environment building

3. Help debug the IP such as DMA, Memory controller, Display Unit


Job Qualification

1. CS or EE Master is preferred, 3~5 years of relevant experiences

2. Altera FPGA verification experiences

3. Familiar with Altera Sigal TAPII

4. Familiar with Oscilloscope, Logic analyzer

5. Familiar with ARM SOC

6. Familiar with Verilog or VHDL

IC人才网原链：http://www.jobic.cn/Html/JobDetails/14083.html
10月份注册简历赢ipad:http://www.jobic.cn/Resume/Register.aspx
邮箱：jobic_cn@126.com
电话：0755-26490606

strivenbu

灿芯又不招人 整天那么多招聘信息

jessie1

谁说不招人。刚和我们www.jobic.cn 合作不久，职位也是近期刚发布上去的;怎么会不招人呢

jessie1

支持一下～～～～

apacheda

招人的，上个星期他们个我发了一个Offer

jessie1

恭喜恭喜啊～～

shangyouqiang

又走人了？

helenhappy

什么情况？

Alanni

还不错。

zhuoming

我是灿芯的，还在招。