在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 17929|回复: 65

[资料] multi-mode multi-band RF transceiver for wireless communications

[复制链接]
发表于 2011-6-24 22:16:22 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
Table of Contents
  Contributors.

Preface.
I TRANSCEIVER CONCEPTS AND DESIGN.
1 Software-Defined Radio Front Ends (Jan Craninckx).
1.1 Introduction.
1.2 System-Level Considerations.
1.3 Wideband LO Synthesis.
1.4 Receiver Building Blocks.
1.5 Transmitter Building Blocks.
1.6 Calibration Techniques.
1.7 Full SDR Implementation.
1.8 Conclusions.
2 Software-Defined Transceivers (Gio Cafaro and Bob Stengel).
2.1 Introduction.
2.2 Radio Architectures.
2.3 SDR Building Blocks.
2.4 Example of an SDR Transceiver.
3 Adaptive Multi-Mode RF Front-End Circuits (Aleksandar Tasic).
3.1 Introduction.
3.2 Adaptive Multi-Mode Low-Power Wireless RF IC Design.
3.3 Multi-Mode Receiver Concept.
3.4 Design of a Multi-Mode Adaptive RF Front End.
3.5 Experimental Results for the Image-Reject Down-Converter.
3.6 Conclusions.
4 Precise Delay Alignment Between Amplitude and Phase/Frequency Modulation Paths in a Digital Polar Transmitter (KhurramWaheed and Robert Bogdan Staszewski).
4.1 Introduction.
4.2 RF Polar Transmitter in Nanoscale CMOS.
4.3 Amplitude and Phase Modulation.
4.4 Mechanisms to Achieve Subnanosecond Amplitude and Phase Modulation Path Alignments.
4.5 Precise Alignment of Multi-Rate Direct and Reference Point Data.
5 Overview of Front-End RF Passive Integration into SoCs (Hooman Darabi).
5.1 Introduction.
5.2 The Concept of a Receiver Translational Loop.
5.3 Feedforward Loop Nonideal Effects.
5.4 Feedforward Receiver Circuit Implementations.
5.5 Feedforward Receiver Experimental Results.
5.6 Feedback Notch Filtering for a WCDMA Transmitter.
5.7 Feedback-Based Transmitter Stability Analysis.
5.8 Impacts of Nonidealities in Feedback-Based Transmission.
5.9 Transmitter Building Blocks.
5.10 Feedback-Based Transmitter Measurement Results.
5.11 Conclusions and Discussion.
6 ADCs and DACs for Software-Defined Radio (Michiel Steyaert, Pieter Palmers, and Koen Cornelissens).
6.1 Introduction.
6.2 ADC and DAC Requirements in Wireless Systems.
6.3 Multi-Standard Transceiver Architectures.
6.4 Evaluating Reconfigurability.
6.5 ADCs for Software-Defined Radio.
6.6 DACs for Software-Defined Radio.
6.7 Conclusions.
II RECEIVER DESIGN.
7 OFDM Transform-Domain Receivers for Multi-Standard Communications(Sebastian Hoyos).
7.1 Introduction.
7.2 Transform-Domain Receiver Background.
7.3 Transform-Domain Sampling Receiver.
7.4 Digital Baseband Design for the TD Receiver.
7.5 A Comparative Study.
7.6 Simulations.
7.7 Gain–Bandwidth Product Requirement for an Op-Amp in a Charge-Sampling Circuit.
7.8 Sparsity of (GHG)−1.
7.9 Applications.
7.10 Conclusions.
8 Discrete-Time Processing of RF Signals (RenaldiWinoto and Borivoje Nikolic).
8.1 Introduction.
8.2 Scaling of an MOS Switch.
8.3 Sampling Mixer.
8.4 Filter Synthesis.
8.5 Noise in Switched-Capacitor Filters.
8.6 Circuit-Design Considerations.
8.7 Perspective and Outlook.
9 Oversampled ADC Using VCO-Based Quantizers (MatthewZ. Straayer and MichaelH.Perrott).
9.1 Introduction.
9.2 VCO-Quantizer Background.
9.3 SNDR Limitations for VCO-Based Quantization.
9.4 VCO Quantizer -ADC Architecture.
9.5 Prototype -ADC Example with a VCO Quantizer.
9.6 Conclusions.
References.
10 Reduced External Hardware and Reconfigurable RF Receiver Front Ends for Wireless Mobile Terminals (Naveen K. Yanduru).
10.1 Introduction.
10.2 Mobile Terminal Challenges.
10.3 Research Directions Toward a Multi-Band Receiver.
10.4 Multi-Mode Receiver Principles and RF System Analysis for a W-CDMA Receiver.
10.5 W-CDMA, GSM/GPRS/EDGE Receiver Front End Without an Interstage SAW Filter.
10.6 Highly Integrated GPS Front End for Cellular Applications in 90-nm CMOS.
10.7 RX Front-End Performance Comparison.
11 Digitally Enhanced Alternate Path Linearization of RF Receivers (Edward A.Keehr and AliHajimiri).
11.1 Introduction.
11.2 Adaptive Feedforward Error Cancellation.
11.3 Architectural Concepts.
11.4 Alternate Feedforward Path Block Design Considerations.
11.5 Experimental Design of an Adaptively Linearized UMTS Receiver.
11.6 Experimental Results of an Adaptively Linearized UMTS Receiver.
11.7 Conclusions.
III TRANSMITTER TECHNIQUES.
12 Linearity and Efficiency Strategies for Next-Generation Wireless Communications (Lawrence Larson,Peter Asbeck, and Donald Kimball).
12.1 Introduction.
12.2 Power Amplifier Function.
12.3 Power Amplifier Efficiency Enhancement.
12.4 Techniques for Linearity Enhancement.
12.5 Conclusions.
13 CMOS RF Power Amplifiers for Mobile Communications (Patrick Reynaert).
13.1 Introduction.
13.2 Challenges.
13.3 Low Supply Voltage.
13.4 Average Efficiency, Dynamic Range, and Linearity.
13.5 Polar Modulation.
13.6 Distortion in a Polar-Modulated Power Amplifier.
13.7 Design and Implementation of a Polar-Modulated Power Amplifier.
13.8 Conclusions.
14 Digitally Assisted RF Architectures: Two Illustrative Designs (Joel L. Dawson).
14.1 Introduction.
14.2 Cartesian Feedback: The Analog Problem.
14.3 Digital Assistance for Cartesian Feedback.
14.4 Multipliers, Squarers, Mixers, and VGAs: The Analog Problem.
14.5 Digital Assistance for Analog Multipliers.
14.6 Summary.
Appendix: Stability Analysis for Cartesian Feedback Systems.
IV DIGITAL SIGNAL PROCESSING FOR RF TRANSCEIVERS.
15 RF Impairment Compensation for Future Radio Systems (Mikko Valkama).
15.1 Introduction and Motivation.
15.2 Typical RF Impairments.
15.3 Impairment Mitigation Principles.
15.4 Case Studies in I/Q Imbalance Compensation.
15.5 Conclusions.
16 Techniques for the Analysis of Digital Bang-Bang PLLs (Nicola DaDalt).
16.1 Introduction.
16.2 Digital Bang-Bang PLL Architecture.
16.3 Analysis of the Nonlinear Dynamics of the BBPLL.
16.4 Analysis of the BBPLL with Markov Chains.
16.5 Linearization of the BBPLL.
16.6 Comparison of Measurements and Models.
17 Low-Power Spectrum Processors for Cognitive Radios (Joy Laskar andKyutae Lim).
17.1 Introduction.
17.2 Paradigm Shift from SDR to CR.
17.3 Challenge and Trends in RFIC/System.
17.4 Analog Signal Processing.
17.5 Spectrum Sensing.
17.6 Multi-Resolution Spectrum Sensing.
17.7 MRSS Performance.
17.8 Conclusions.
References.
Index.


abbr_17e906536010eae4d4d94e5607c5d799.rar

14.31 MB, 下载次数: 1002 , 下载积分: 资产 -5 信元, 下载支出 5 信元

part1

abbr_e0cf589878f29f1c7cea84f6411a28d9.rar

6.43 MB, 下载次数: 594 , 下载积分: 资产 -3 信元, 下载支出 3 信元

part2

 楼主| 发表于 2011-6-24 23:24:59 | 显示全部楼层
同时求下面书
《CMOS Analog Integrated Circuits: High-Speed and Power-Efficient Design》
Price:  £89.00
Cat. #:  K12557
ISBN:  9781439854914
ISBN 10:  1439854912
Publication Date:  May 24, 2011
Number of Pages:  925

Discription:

Features
Covers state-of-the-art CMOS integrated-circuit processes
Describes high-speed and power -efficient architectures for analog building blocks
Provides open-ended circuit design case studies
Emphasizes practical aspects relevant to integrated circuit implementations
Analyzes architectures and performance limitation issues affecting the circuit operation

Summary
With particular emphasis on the development of basic analog building blocks, this book shows how to design CMOS analog integrated circuits with improved electrical performance, providing up-to-date coverage of design techniques and circuit architectures that are useful not only for the analog section but also for the digital section of the chip. Highlighting various design challenges, the text offers a complete understanding of architectural- and transistor-level design issues of analog integrated circuits. The author describes important trends in the design of high-speed and power-efficient front-end analog circuits, which can be used to interface modern digital signal processors.


Table of Contents


Introduction

MOS Transistors

Physical Design of MOS Integrated Circuits

Bias and Current Reference Circuits

CMOS Amplifiers

Non-linear Analog Components

Continuous-Time Circuits

Switched-Capacitor Circuits

Data Converter Principles

Nyquist Digital-to-Analog Converters

Nyquist Analog-to-Digital converters

Oversampling Data Converters

Circuits for Clock Signal Generation and Synchronization

Appendix



Author Biography
Tertulien Ndjountche is a senior member of the Institute of Electrical and Electronics Engineers (IEEE) and an member of Professional Engineer Ontario (PEO) in Gatineau, Canada.
发表于 2011-6-25 09:24:42 | 显示全部楼层
kankan...
发表于 2011-6-25 15:55:51 | 显示全部楼层
非常感谢
发表于 2011-6-25 18:36:02 | 显示全部楼层
谢谢分享。
发表于 2011-6-27 10:06:39 | 显示全部楼层
下来看看,谢谢。
发表于 2011-6-30 13:45:20 | 显示全部楼层
回复 1# langtaosha
发表于 2011-7-9 05:41:48 | 显示全部楼层
Craninckx的东西要顶
发表于 2012-10-9 21:45:25 | 显示全部楼层
这个解压不了啊
发表于 2013-3-28 16:14:15 | 显示全部楼层
妈的,骗信元的,根本解压不了!
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /2 下一条


小黑屋| 手机版| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-11-28 22:35 , Processed in 0.024264 second(s), 9 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表