第一,link之后,check design出现这样的warning是怎么回事?如何查错?
Warning: In design 'shift', cell 'B_4' does not drive any nets. (LINT-1)
第二,出现输出悬空的线是否要紧?应该如何避免?
比如一个乘法器4位*4位输出8位,但我只需要前4位,后四位wire型悬空会影响后端么?
Warning: verilog writer has added 32 nets to module shift using SYNOPSYS_UNCONNECTED_ as prefix. Please use the change_names command to make the correct changes before invoking the verilog writer. (VO-11)