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楼主 |
发表于 2010-9-20 08:37:59
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原程序:
module demo(
input HCLK,
input S_HRET,
input i_regs,
output Relay_ON
);
reg [1:0] Prescale;
reg [11:0] Dcounter;
parameter Utmost = 12'h800;
always @(posedge HCLK)
begin
if (~S_HRET)
Prescale <= 2'h0;
else
Prescale <= Prescale +1;
end
always @(posedge Prescale[1])
begin
begin
if (~S_HRET)
Dcounter <= 12'hff0;
else if (Dcounter <= Utmost)
Dcounter <= Dcouter+1;
end
assign Relay_ON = (Dcounter < Utmost) || i_regs;
endmodule |
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