HV ESD protection

jian1712 · 发表于 2010-5-25 18:05:06

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本帖最后由 jian1712 于 2010-5-25 18:07 编辑

ESD protection solutions for high voltage technologies.pdf
abstract
There is a trend to revive mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD design windows, NMOS degradation problems and the creation of unexpectedly weak parasitic devices. Different case studies are presented for ESD protection based on latch-up immune SCR devices.

ESD protection solutions for high voltage technologies.pdf (729.12 KB , 下载次数: 641 )

analogmind · 发表于 2010-5-25 21:19:50

楼主，能不能再多发点HV ESD方面的论文啊，多谢了，我手头很少。

feel100 · 发表于 2010-5-25 22:46:19

这个有用,谢了

vincentlu · 发表于 2010-5-26 08:53:26

thanks!

mycelldevice · 发表于 2010-5-26 09:17:01

ding ni

allantseng · 发表于 2010-5-26 10:14:54

It is good for my job

jian1712 · 发表于 2010-5-26 12:39:22

2# analogmind

http://www.eetop.cn/bbs/viewthread.php?tid=231549
1. High-voltage nLDMOS in waffle-layout style with body-injected technique for ESD protection
2. Investigation on the validity of holding voltage in high-voltage devices measured by transmission-line-pulsing (TLP)
3. Source-side engineering to increase holding voltage of LDMOS in a 0.5-um 16-V BCD technology to avoid latch-up failure
4. Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection
5. Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration

alexpanait · 发表于 2010-5-26 13:38:35

nice site.

navyhu · 发表于 2010-5-26 14:07:12

take a look
thanks for sharing

雨田 · 发表于 2010-5-26 15:24:24

thanks for sharing

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