modeling and simulation of jitter in PLL

pch032

This  paper  presents  a  methodology  to  simulate,  at  the
system-level, substrate noise coupling to phase-locked loop
(PLL)  circuits.  Macro  models  of  the  noise  coupling  to  the
PLL  are  proposed  based  on  the  concept  of  an  impulse
sensitivity  function  (ISF).

chujn

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sunward

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hsn

thank you...

pgdn

mei shen me yong a

jyhking

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jyhking

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smithe

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bloodylord

谢谢分享~

hnwulei

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