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ESD robustness of thin-film devices with different
layout structures in LTPS technology
Chih-Kang Deng, Ming-Dou Ker
Nanoelectronics and Gigascale Systems Laboratory, Institute of Electronics, National Chiao-Tung University,
1001 Ta-Hsueh Road, Hsinchu, Taiwan, ROC
Received 1 August 2005; received in revised form 1 November 2005
Abstract
Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-achip
(SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should
meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design
concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS
transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail
ESD clamp circuits are presented and discussed |
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发表于 2007-9-6 16:36:36
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