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发表于 2008-8-15 15:23:14
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Actually, some designers put Cc before Rz to the 2nd stage for some reason.
Eg:the 0.5V OTA in "A 0.5V 8bit 10Ms/s Pipelined ADC in 90nm CMOS" JSSC pp787-795, April 2008. See fig. 4. This paper doesn't tell the exact reason, though.
However, I think it is because the non-dominant pole is formed from CL and if Rz is put after Cc, it somehow "isolates" the parasitic capacitance from Cc. Thus it wont affect the non-dominant pole. |
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