[PDF BOOK] SKEW-TOLERANT CIRCUIT DESIGN

jiangfire

突然发现eetop居然没有这书，就传上来了

SKEW-TOLERANT CIRCUIT DESIGN
David Harris
February 1999

基本上是讲N phase overlap clock的分析和design methodology，大概只有高速到变态的运算单元用得到这种设计方法
也许对于一般的公司来说用到的机会不多，
但是是很好的背景知识

Table of Contents
Chapter 1 Skew-Tolerant Circuit Design......................................................................1
1.1 Overhead in Flip-Flop Systems........................................................................................... 1
1.2 Throughput and Latency Trends ......................................................................................... 4
1.2.1 Impact of Overhead on Throughput and Latency ................................................. 5
1.2.2 Historical Trends................................................................................................... 6
1.2.3 Future Predictions ................................................................................................. 9
1.2.4 Conclusions......................................................................................................... 10
1.3 Skew-Tolerant Static Circuits............................................................................................ 10
1.4 Domino Circuits ................................................................................................................ 12
1.4.1 Domino Gate Operation...................................................................................... 13
1.4.2 Traditional Domino Clocking ............................................................................. 18
1.4.3 Skew-Tolerant Domino ....................................................................................... 19
1.5 A Look Ahead ................................................................................................................... 22
Chapter 2 Skew-Tolerant Domino Circuits ................................................................24
2.1 Skew-Tolerant Domino Timing......................................................................................... 24
2.1.1 General Timing Constraints ................................................................................ 25
2.1.2 Clock Domains.................................................................................................... 28
2.1.3 50% Duty Cycle.................................................................................................. 30
2.1.4 Single Gate per Phase ......................................................................................... 31
2.1.5 Min-Delay Constraints........................................................................................ 32
2.1.6 Recommendations and Design Issues................................................................. 34
2.2 Simulation Results............................................................................................................. 36
2.3 Summary ........................................................................................................................... 38
Chapter 3 Circuit Methodology..................................................................................39
3.1 Static / Domino Interface .................................................................................................. 40
3.1.1 Static to Domino Interface .................................................................................. 40
3.1.2 Domino to Static Interface .................................................................................. 41
3.1.3 Timing Types ...................................................................................................... 43
3.1.4 Qualified Clocks.................................................................................................. 57
3.1.5 Min-Delay Checks .............................................................................................. 58
3.2.1 Latch Design ....................................................................................................... 61
3.2.2 Domino Gate Design........................................................................................... 62
3.2.3 Special Structures................................................................................................ 63
3.3 Testability .......................................................................................................................... 65
3.3.1 Static Logic ......................................................................................................... 66
3.3.2 Domino Logic ..................................................................................................... 67
3.4 Summary ........................................................................................................................... 70
Chapter 4 Clocking.....................................................................................................71
4.1 Clock Waveforms .............................................................................................................. 72
4.1.1 Physical Clock Definitions.................................................................................. 72
4.1.2 Clock Skew......................................................................................................... 74
4.1.3 Clock Domains.................................................................................................... 76
4.2 Skew-Tolerant Domino Clock Generation ........................................................................ 77
4.2.1 Delay Line Clock Generators.............................................................................. 78
4.2.2 Feedback Clock Generators ................................................................................ 84
4.2.3 Putting It All Together ........................................................................................ 86
4.3 Summary ........................................................................................................................... 87
Chapter 5 Timing Analysis.........................................................................................89
5.1 Background.......................................................................................................................90
5.2 Timing Analysis without Clock Skew ...............................................................................91
5.3 Timing Analysis with Clock Skew ....................................................................................94
5.3.1 Single Skew Formulation ....................................................................................95
5.3.2 Exact Skew Formulation......................................................................................96
5.3.3 Clock Domain Formulation.................................................................................98
5.3.4 Example.............................................................................................................102
5.4 Extension to Flip-Flops and Domino Circuits .................................................................103
5.4.1 Flip-Flops ..........................................................................................................103
5.4.2 Domino Gates....................................................................................................104
5.5 Min-Delay........................................................................................................................105
5.6 A Verification Algorithm .................................................................................................107
5.7 Results.............................................................................................................................110
5.8 Summary.........................................................................................................................112
5.9 Appendix: Timing Constraints.........................................................................................112
5.9.1 Skewless Formulation........................................................................................112
5.9.2 Single Skew Formulation ..................................................................................113
5.9.3 Exact Formulation .............................................................................................113
5.9.4 Clock Domain Formulation...............................................................................115
Chapter 6 Conclusions..............................................................................................116
Bibliography 119

kaoruzhu

thanks

lhyi

Thanks

austin_lin

Thanks!

xudeqiang

太强了，这么好的书都能搞到

charlie11

thank you

wangdx

不错，

xichen07

谢谢lz

janischen

skew 是很重要的課題
感謝你的分享

pleely

楼主好人呀