最新的SystemVerilogAssertions培训实验，请版主评精

lengyueguxing · 发表于 2012-12-4 12:46:51

回复 4# m222222

XIEXIEFENXIANG

ID2007 · 发表于 2012-12-13 21:36:29

Lab Ojectives: This is a review lab, looking at concepts covered in the
begginers assertion seminar. To bind a checker from the VCS checker library
to the DMA engine. Also write simple assertions to check the control signals
in the DMA engine.

mildmind · 发表于 2012-12-15 21:53:15

谢谢分享

seulk · 发表于 2012-12-19 09:13:25

谢谢LOUZHU

seulk · 发表于 2012-12-19 09:14:35

正在找断言方面的资料，谢谢

ekoyosta · 发表于 2012-12-19 16:02:58

Thanks for sharing

heeda · 发表于 2012-12-20 21:16:38

ddddd

heeda · 发表于 2012-12-20 21:16:59

dddlll

xishuai · 发表于 2012-12-21 18:50:40

这个要拿来看看了，哈哈

secant0711 · 发表于 2012-12-24 15:04:10

thx for sharing

最新的SystemVerilogAssertions培训实验，请版主评精

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