PrimieTime做fix eco timing时，为啥修sequential cell会影响clock tree timing呢

ZTZ-99

PrimieTime man fix_eco_timing有这么段内容：

       -cell_type combinational | sequential | clock_network
              Specifies the type of cells to be modified for timing fixing:

              o combinational (the default) - Fixing is performed by sizing or
                inserting combinational logic cells in the data path.
              o sequential - Fixing is performed by sizing sequential cells to
                fix violations at the sequential cell's input or  output  pin.
                Only  the size_cell fixing method (-methods size_cell) is sup-
                ported for this type of fixing.
              o clock_network - Fixing is performed  by  sizing  or  inserting
                combinational  cells  in  the  clock network, thereby changing
                clock arrival times.

              You can specify just one of these options, or both combinational
              and sequential together to fix both cell types simultaneously.

              The   sequential   and   clock_network  type  modifications  can
              adversely affect clock tree timing, so you should  try  combina-
              tional  type  fixing first and only apply the other types after-
              ward if needed.



clock tree不是由一堆特殊的INV或者BUFF组成的吗？为啥修 sequential cell会影响clock tree呢？

Challensys

resize DFF 会导致时钟树 leaf 的 load 改变，从而改变时钟树同一 leaf 上其他 DFF 的时序

aqiqiqiqi

icg属于时序逻辑，可能size up了icg

dingyisuper1

楼上回答终结了