轨到轨运放增益

模集新手

小弟最近在做一个轨到轨的运放，输入级采用1：3电流镜，输出级是classAB，我仿真的开环增益在输入共模电压靠近gnd和VDD两侧会比输入共模电压在中间范围的时候有较大的偏差，想请教一下我是应该是增加输入级的跨导还是优化共源共栅负载提高输出电阻使输出随着共模电压的变化不会有很大的偏差。

LoktikVJ

100% problem with biasing for your cascodes
M30 Vds=241.9mV, Vdssat=182.3mV, to close, you need more margin Vds>1.5-3*Vdsat
M31 Vds=253mV, Vdssat=294mV, to close, you need more margin Vds>1.5-3*Vdsat
M43 Vds=175mV, Vdssat=190mV, to close, you need more margin Vds>1.5-3*Vdsat
+ you need to check you input pair adjusted current for diff amp common mode voltages

LoktikVJ

problem with gain -> problem with transistor biasing

模集新手

   

LoktikVJ 发表于 2025-8-29 22:52
100% problem with biasing for your cascodes
M30 Vds=241.9mV, Vdssat=182.3mV, to close, you need more ...

thanks for your advice

模集新手

   

LoktikVJ 发表于 2025-8-29 22:52
100% problem with biasing for your cascodes
M30 Vds=241.9mV, Vdssat=182.3mV, to close, you need more ...

I change my bias and make sure that all my transistor work in region2（Vcm0~1.8）the VDD is 1.8V total gm is quiet stable，I still have the problem of the gain. My question is :the output current of classAB isn‘t stable what can I do to fix this ，is it still the problem of cascode bias？