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Cadence RAK : JasperGold Design Bring-up Rapid Adoption Kit
Course Objectives
- Describe a methodology for the initial bring-up of RTL designs using formal verification instead a simulation testbench
- Show features of JasperGold that can help with RTL design bring-up
- Demonstrate the types of static analysis that can be performed, including clock and reset analysis
- Become familiar with a methodology that can help give you confidence that your design is functioning as expected
- Learn about features of JasperGold Visualize that help you explore design behavior
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