|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
×
REPORT FILE NAME: 4to1and.lvs.reportLAYOUT NAME: 4to1and.sp ('4to1and')
SOURCE NAME: /home/rocky/netlist/4to1and.cdl ('4to1and')
RULE FILE: _lvs.calibre_
CREATION TIME: Sun Apr 13 12:52:42 2025
CURRENT DIRECTORY: /home/rocky/result
USER NAME: rocky
CALIBRE VERSION: v2023.2_16.9 Tue Apr 4 17:40:41 PDT 2023
OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of ports.
Error: Different numbers of nets.
Error: Different numbers of instances.
Error: Connectivity errors.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT 4to1and 4to1and
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME "VD33" "AVDDB" "AVD33" "DVDD" "AVD33B" "VDDG" "AVDDG" "AVD33G" "AVDDBG" "VDD5V"
"TAVDDPST" "TAVD33PST" "VDWELL" "AVDWELL" "AVDDR" "VDDSA" "TAVDD" "AVD33R" "VD33WELL"
"TAVD33" "VDDPST" "AVD33WELL" "VDD" "AVDD"
LVS GROUND NAME "DVSS" "AVS33R" "VSSG" "AVSSG" "AVSSBG" "TAVSSPST" "AVSSR" "VS33" "AVS33" "TAVSS"
"AVS33B" "VSSPST" "VSSUB" "AVSSUB" "AVS33G" "GND" "VS33SUB" "AGND" "AVS33SUB" "VSS"
"AVSS" "AVSSB"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES NONE
// LVS HCELL REPORT
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE YES
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS FLATTEN INSIDE CELL NO
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS RELAX INITIAL CPOINTS NONE
LVS REVERSE WL NO
// LVS NETLIST FILTER DEVICES NO
// LVS PRESERVE BOX PORTS NO
LVS SPICE PREFER PINS YES
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
// LVS SPICE EXCLUDE CELL SOURCE
// LVS SPICE EXCLUDE CELL LAYOUT
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LAYOUT CASE NO
SOURCE CASE NO
LVS COMPARE CASE NO
LVS COMPARE CASE STRICT NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 1000
LVS PROPERTY RESOLUTION MAXIMUM 32
// LVS SIGNATURE MAXIMUM
LVS FILTER UNUSED OPTION AB RC RE RG
LVS REPORT OPTION S
LVS REPORT UNITS YES
LVS SWAPPABLE HCELL PINS GENERAL
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// LVS IGNORE DEVICE PIN
// LVS PREFER NETS FILTER SOURCE
// LVS PREFER NETS FILTER LAYOUT
LVS PREFER PORT NETS NO
LVS EXPAND ON ERROR NO
LVS EXPAND AMBIGUOUSLY HIGH SHORTED HCELLS NO
// Reduction
LVS REDUCE SERIES MOS NO
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCE rpodrpo_m PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rpodrpo_m SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rnodrpo_m PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rnodrpo_m SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rpodw_m PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rpodw_m SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rnodw_m PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rnodw_m SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rnwod_m PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rnwod_m SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rpod_m PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rpod_m SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rnod_m PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rnod_m SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rnpo1rpo_dis PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rnpo1rpo_dis SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rppo1rpo_dis PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rppo1rpo_dis SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rnpo1w_dis PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rnpo1w_dis SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rppo1w_dis PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rppo1w_dis SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rppo1_dis PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rppo1_dis SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rnpo1_dis PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rnpo1_dis SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCE rppolyhri_dis PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE rppolyhri_dis SERIES PLUS MINUS [ TOLERANCE W 0 ]
LVS REDUCTION PRIORITY PARALLEL
LVS SHORT EQUIVALENT NODES NO
// Trace Property
TRACE PROPERTY mn(n2) l l 0
TRACE PROPERTY mn(n2) w w 0
TRACE PROPERTY mn(nb) l l 0
TRACE PROPERTY mn(nb) w w 0
TRACE PROPERTY mn(nd) l l 0
TRACE PROPERTY mn(nd) w w 0
TRACE PROPERTY mn(nl) l l 0
TRACE PROPERTY mn(nl) w w 0
TRACE PROPERTY mn(nn) l l 0
TRACE PROPERTY mn(nn) w w 0
TRACE PROPERTY mn(n) l l 0
TRACE PROPERTY mn(n) w w 0
TRACE PROPERTY mn(n1) l l 0
TRACE PROPERTY mn(n1) w w 0
TRACE PROPERTY mn(na) l l 0
TRACE PROPERTY mn(na) w w 0
TRACE PROPERTY mp(p) l l 0
TRACE PROPERTY mp(p) w w 0
TRACE PROPERTY mp(pa) l l 0
TRACE PROPERTY mp(pa) w w 0
TRACE PROPERTY mp(pd) l l 0
TRACE PROPERTY mp(pd) w w 0
TRACE PROPERTY q(p1) a a 0
TRACE PROPERTY q(pv) a a 0
TRACE PROPERTY q(nv) a a 0
TRACE PROPERTY d(dn) a a 0
TRACE PROPERTY d(dw) a a 0
TRACE PROPERTY d(dp) a a 0
TRACE PROPERTY d(d1) a a 0
TRACE PROPERTY d(d2) a a 0
TRACE PROPERTY d(d3) a a 0
TRACE PROPERTY r(nr) r r 0
TRACE PROPERTY r(m3) r r 0
TRACE PROPERTY r(ns) r r 0
TRACE PROPERTY r(mt) r r 0
TRACE PROPERTY r(pr) r r 0
TRACE PROPERTY r(ps) r r 0
TRACE PROPERTY r(wr) r r 0
TRACE PROPERTY r(m1) r r 0
TRACE PROPERTY r(lr) r r 0
TRACE PROPERTY r(m2) r r 0
TRACE PROPERTY c(m3) c c 0
TRACE PROPERTY rnpo1rpo_dis w w 0
TRACE PROPERTY rnpo1rpo_dis l l 0
TRACE PROPERTY rppolyhri_rf w w 0
TRACE PROPERTY rppolyhri_rf l l 0
TRACE PROPERTY moscap_rf33 g g 0
TRACE PROPERTY moscap_rf33 b b 0
TRACE PROPERTY pmos_rf33_nw lr lr 0
TRACE PROPERTY pmos_rf33_nw wr wr 0
TRACE PROPERTY pmos_rf33_nw nr nr 0
TRACE PROPERTY rpod_m w w 0
TRACE PROPERTY rpod_m l l 0
TRACE PROPERTY rppo1rpo_dis w w 0
TRACE PROPERTY rppo1rpo_dis l l 0
TRACE PROPERTY rppolyhri_dis w w 0
TRACE PROPERTY rppolyhri_dis l l 0
TRACE PROPERTY rppoly_rf w w 0
TRACE PROPERTY rppoly_rf l l 0
TRACE PROPERTY rppolywo_rf w w 0
TRACE PROPERTY rppolywo_rf l l 0
TRACE PROPERTY mimcap_shield lt lt 0
TRACE PROPERTY mimcap_shield wt wt 0
TRACE PROPERTY mimcap_wos lt lt 0
TRACE PROPERTY mimcap_wos wt wt 0
TRACE PROPERTY nmoscap lr lr 0
TRACE PROPERTY nmoscap wr wr 0
TRACE PROPERTY nmoscap mr mr 0
TRACE PROPERTY rnodw_m w w 0
TRACE PROPERTY rnodw_m l l 0
TRACE PROPERTY nmoscap_33 lr lr 0
TRACE PROPERTY nmoscap_33 wr wr 0
TRACE PROPERTY nmoscap_33 mr mr 0
TRACE PROPERTY lincap lr lr 0
TRACE PROPERTY lincap wr wr 0
TRACE PROPERTY lincap mr mr 0
TRACE PROPERTY rpodw_m w w 0
TRACE PROPERTY rpodw_m l l 0
TRACE PROPERTY spiral_s2_sym_ct lay lay 0
TRACE PROPERTY spiral_s2_sym_ct w w 0
TRACE PROPERTY spiral_s2_sym_ct s s 0
TRACE PROPERTY spiral_s2_sym_ct nr nr 0
TRACE PROPERTY spiral_s2_sym_ct rad rad 0
TRACE PROPERTY spiral_s3_sym_ct lay lay 0
TRACE PROPERTY spiral_s3_sym_ct w w 0
TRACE PROPERTY spiral_s3_sym_ct s s 0
TRACE PROPERTY spiral_s3_sym_ct nr nr 0
TRACE PROPERTY spiral_s3_sym_ct rad rad 0
TRACE PROPERTY spiral_s2_sym lay lay 0
TRACE PROPERTY spiral_s2_sym w w 0
TRACE PROPERTY spiral_s2_sym s s 0
TRACE PROPERTY spiral_s2_sym nr nr 0
TRACE PROPERTY spiral_s2_sym rad rad 0
TRACE PROPERTY spiral_s3_sym lay lay 0
TRACE PROPERTY spiral_s3_sym w w 0
TRACE PROPERTY spiral_s3_sym s s 0
TRACE PROPERTY spiral_s3_sym nr nr 0
TRACE PROPERTY spiral_s3_sym rad rad 0
TRACE PROPERTY xjvar_w40 nr nr 0
TRACE PROPERTY xjvar_w40 w w 0
TRACE PROPERTY rnpo1w_dis w w 0
TRACE PROPERTY rnpo1w_dis l l 0
TRACE PROPERTY rppo1w_dis w w 0
TRACE PROPERTY rppo1w_dis l l 0
TRACE PROPERTY rnpo1_dis w w 0
TRACE PROPERTY rnpo1_dis l l 0
TRACE PROPERTY rnodrpo_m w w 0
TRACE PROPERTY rnodrpo_m l l 0
TRACE PROPERTY rppo1_dis w w 0
TRACE PROPERTY rppo1_dis l l 0
TRACE PROPERTY rpodrpo_m w w 0
TRACE PROPERTY rpodrpo_m l l 0
TRACE PROPERTY xjvar_nr36 nr nr 0
TRACE PROPERTY xjvar_nr36 w w 0
TRACE PROPERTY nmos_rf lr lr 0
TRACE PROPERTY nmos_rf wr wr 0
TRACE PROPERTY nmos_rf nr nr 0
TRACE PROPERTY spiral_s2_std lay lay 0
TRACE PROPERTY spiral_s2_std w w 0
TRACE PROPERTY spiral_s2_std s s 0
TRACE PROPERTY spiral_s2_std nr nr 0
TRACE PROPERTY spiral_s2_std rad rad 0
TRACE PROPERTY spiral_s3_std lay lay 0
TRACE PROPERTY spiral_s3_std w w 0
TRACE PROPERTY spiral_s3_std s s 0
TRACE PROPERTY spiral_s3_std nr nr 0
TRACE PROPERTY spiral_s3_std rad rad 0
TRACE PROPERTY pmos_rf lr lr 0
TRACE PROPERTY pmos_rf wr wr 0
TRACE PROPERTY pmos_rf nr nr 0
TRACE PROPERTY rnwod_m w w 0
TRACE PROPERTY rnwod_m l l 0
TRACE PROPERTY pmos_rf_nw lr lr 0
TRACE PROPERTY pmos_rf_nw wr wr 0
TRACE PROPERTY pmos_rf_nw nr nr 0
TRACE PROPERTY nmos_rf33 lr lr 0
TRACE PROPERTY nmos_rf33 wr wr 0
TRACE PROPERTY nmos_rf33 nr nr 0
TRACE PROPERTY moscap_rf g g 0
TRACE PROPERTY moscap_rf b b 0
TRACE PROPERTY pmos_rf33 lr lr 0
TRACE PROPERTY pmos_rf33 wr wr 0
TRACE PROPERTY pmos_rf33 nr nr 0
TRACE PROPERTY rnod_m w w 0
TRACE PROPERTY rnod_m l l 0
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of ports (see below).
Error: Different numbers of nets (see below).
Error: Different numbers of instances (see below).
Error: Connectivity errors.
LAYOUT CELL NAME: 4to1and
SOURCE CELL NAME: 4to1and
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 0 7 *
Nets: 12 11 *
Instances: 5 5 MN (4 pins)
5 5 MP (4 pins)
------ ------
Total Inst: 10 10
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 0 7 *
Nets: 9 11 *
Instances: 0 3 * MN (4 pins)
4 3 * MP (4 pins)
1 2 * _invv (4 pins)
1 0 * _smn4v (6 pins)
------ ------
Total Inst: 6 8
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 Net 12 ** no similar net **
--------------------------------------------------------------------------------------------------------------
2 Net 9 ** no similar net **
--------------------------------------------------------------------------------------------------------------
3 Net 3 ** no similar net **
--------------------------------------------------------------------------------------------------------------
4 Net 2 ** no similar net **
--------------------------------------------------------------------------------------------------------------
5 Net 5 ** no similar net **
--------------------------------------------------------------------------------------------------------------
6 Net 7 ** no similar net **
--------------------------------------------------------------------------------------------------------------
7 Net 10 ** no similar net **
--------------------------------------------------------------------------------------------------------------
8 Net 11 ** no similar net **
--------------------------------------------------------------------------------------------------------------
9 Net 1 ** no similar net **
--------------------------------------------------------------------------------------------------------------
10 ** no similar net ** GND
--------------------------------------------------------------------------------------------------------------
11 ** no similar net ** VCC
--------------------------------------------------------------------------------------------------------------
12 ** no similar net ** VIN1
--------------------------------------------------------------------------------------------------------------
13 ** no similar net ** VIN2
--------------------------------------------------------------------------------------------------------------
14 ** no similar net ** VIN3
--------------------------------------------------------------------------------------------------------------
15 ** no similar net ** VIN4
--------------------------------------------------------------------------------------------------------------
16 ** no similar net ** VOUT1
--------------------------------------------------------------------------------------------------------------
17 ** no similar net ** net4
--------------------------------------------------------------------------------------------------------------
18 ** no similar net ** net2
--------------------------------------------------------------------------------------------------------------
19 ** no similar net ** net1
--------------------------------------------------------------------------------------------------------------
20 ** no similar net ** net3
**************************************************************************************************************
INCORRECT PORTS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
21 ** missing port ** GND on net: GND
22 ** missing port ** VCC on net: VCC
23 ** missing port ** VIN1 on net: VIN1
24 ** missing port ** VIN2 on net: VIN2
25 ** missing port ** VIN3 on net: VIN3
26 ** missing port ** VIN4 on net: VIN4
27 ** missing port ** VOUT1 on net: VOUT1
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
28 (_smn4v) ** missing injected instance **
Devices:
X8/M0(7.680,-7.680) MN(N)
X7/M0(5.680,-7.680) MN(N)
X6/M0(3.680,-7.680) MN(N)
X5/M0(1.680,-7.680) MN(N)
--------------------------------------------------------------------------------------------------------------
29 ** missing instance ** MM3 MN(N)
--------------------------------------------------------------------------------------------------------------
30 ** missing instance ** MM5 MN(N)
--------------------------------------------------------------------------------------------------------------
31 ** missing instance ** MM4 MN(N)
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 0 0 0 7
Nets: 0 0 9 11
Instances: 0 0 0 3 MN(N)
0 0 4 3 MP(P)
0 0 1 2 _invv
0 0 1 0 _smn4v
------- ------- --------- ---------
Total Inst: 0 0 6 8
**************************************************************************************************************
UNMATCHED OBJECTS
LAYOUT SOURCE
**************************************************************************************************************
X0/M0(1.500,-4.600) MP(P) ** unmatched instance **
X1/M0(3.680,-2.600) MP(P) ** unmatched instance **
X2/M0(5.500,-4.600) MP(P) ** unmatched instance **
X3/M0(7.680,-2.600) MP(P) ** unmatched instance **
--------------------------------------------------------------------------------------------------------------
(_invv) ** unmatched injected instance **
Devices:
X4/M0(9.500,-4.600) MP(P)
X9/M0(9.500,-9.680) MN(N)
--------------------------------------------------------------------------------------------------------------
** unmatched instance ** MM2 MP(P)
** unmatched instance ** MM8 MP(P)
** unmatched instance ** MM1 MP(P)
--------------------------------------------------------------------------------------------------------------
** unmatched injected instance ** (_invv)
Devices:
MM9 MP(P)
MM7 MN(N)
--------------------------------------------------------------------------------------------------------------
** unmatched injected instance ** (_invv)
Devices:
MM0 MP(P)
MM6 MN(N)
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time: 0 sec
Total Elapsed Time: 0 sec
|
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
IP卡
狗仔卡
发表于 2025-4-14 01:19:01
提升卡
沉默卡
喧嚣卡
变色卡
创芯人才网