招聘：数字验证工程师-东南亚

Franky01

本平台专注各类半导体相关职位招聘，IP设计、模拟版图/数字验证/数字后端外包设计，以及MPW&NTO流片服务。

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Requirements:

The candidate is preferred to be MSEE with minimum of 4 years, in digital ASIC/SOC design verification. More experience will be considered as senior engineer or lead.

The candidate should have good understanding on ASIC/SOC design flow and should have:

1. Familiar with one of major verification languages: UVM, C, C++,

SystemVerilog, Verilog

2. Good knowledge of design verification methodology, such as UVM or OVM and coverage driven verification methodology

3. Many experiences with simulation model creation and the testbench build

4. Strong RTL coding with Verilog and familiar with front-end design flow

5. Background in one of the area below will be a strong plus:

a. Strong C/C++ software development experiences for ARM based SoC system

b. Video, display, GPU, DDR, PCIe, USB etc..

6. Be familiar with scripting language, such as Perl, C shell, Makefile.

Franky01

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