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小弟后端新手，用icc做完pr之后在calibre里lvs始终跑不过，求助各位大神指点一下，附部分lvs的report，全部的report放在附件里了，先谢过各位大神
##################################################
## ##
## C A L I B R E S Y S T E M ##
## ##
## L V S R E P O R T ##
## ##
##################################################
REPORT FILE NAME: tag_initial.lvs.report
LAYOUT NAME: tag_initial.sp ('tag_initial')
SOURCE NAME: tag.cdl ('tag')
RULE FILE: cmos013ee.lvs.cal
HCELL FILE: hcell.list
CREATION TIME: Wed Apr 2 18:48:10 2025
CURRENT DIRECTORY: tag
USER NAME: host
CALIBRE VERSION: v2019.3_15.11 Tue Jul 2 12:24:58 PDT 2019
OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Properties missing on instances in source.
Error: Different numbers of ports.
Error: Different numbers of nets.
Error: Different numbers of instances.
Error: Power or ground net missing.
Error: Connectivity errors.
Error: Property errors.
Error: Cells with non-floating extra pins.
Warning: Extra ports in source.
Warning: Ambiguity points were found and resolved arbitrarily.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT ADDFXL ADDFXL
INCORRECT ADDHXL ADDHXL
INCORRECT AND2X1 AND2X1
INCORRECT AND3X1 AND3X1
INCORRECT AND4X1 AND4X1
NOT COMPARED AO21X1 AO21X1
NOT COMPARED AO22X1 AO22X1
NOT COMPARED AOI211X1 AOI211X1
NOT COMPARED AOI211XL AOI211XL
NOT COMPARED AOI21XL AOI21XL
NOT COMPARED AOI221X1 AOI221X1
NOT COMPARED AOI221XL AOI221XL
NOT COMPARED AOI222XL AOI222XL
NOT COMPARED AOI22XL AOI22XL
INCORRECT AOI2BB1X1 AOI2BB1X1
NOT COMPARED AOI2BB2X1 AOI2BB2X1
NOT COMPARED AOI31X1 AOI31X1
NOT COMPARED AOI31XL AOI31XL
NOT COMPARED AOI32XL AOI32XL
NOT COMPARED AOI33XL AOI33XL
INCORRECT CLKBUFX2 CLKBUFX2
NOT COMPARED CLKBUFX20 CLKBUFX20
INCORRECT CLKBUFX3 CLKBUFX3
INCORRECT CLKBUFX4 CLKBUFX4
INCORRECT CLKBUFX6 CLKBUFX6
INCORRECT CLKINVX1 CLKINVX1
NOT COMPARED CLKINVX12 CLKINVX12
NOT COMPARED CLKINVX16 CLKINVX16
INCORRECT CLKINVX2 CLKINVX2
INCORRECT CLKINVX3 CLKINVX3
INCORRECT CLKINVX4 CLKINVX4
NOT COMPARED CLKINVX6 CLKINVX6
NOT COMPARED CLKINVX8 CLKINVX8
INCORRECT DFFHQX8 DFFHQX8
INCORRECT DFFNSRX1 DFFNSRX1
INCORRECT DFFQX1 DFFQX1
INCORRECT DFFRX1 DFFRX1
INCORRECT EDFFX1 EDFFX1
INCORRECT INVX1 INVX1
INCORRECT INVX3 INVX3
INCORRECT MXI2X1 MXI2X1
INCORRECT NAND2BX1 NAND2BX1
INCORRECT NAND2X1 NAND2X1
INCORRECT NAND2X2 NAND2X2
INCORRECT NAND3BX1 NAND3BX1
INCORRECT NAND3X1 NAND3X1
INCORRECT NAND3X2 NAND3X2
INCORRECT NAND4BBXL NAND4BBXL
INCORRECT NAND4BX1 NAND4BX1
INCORRECT NAND4X1 NAND4X1
INCORRECT NOR2BX1 NOR2BX1
INCORRECT NOR2BXL NOR2BXL
INCORRECT NOR2X1 NOR2X1
INCORRECT NOR2X2 NOR2X2
INCORRECT NOR3BXL NOR3BXL
INCORRECT NOR3X1 NOR3X1
INCORRECT NOR3X2 NOR3X2
INCORRECT NOR3XL NOR3XL
INCORRECT NOR4BXL NOR4BXL
INCORRECT NOR4X1 NOR4X1
INCORRECT NOR4XL NOR4XL
NOT COMPARED OA21X1 OA21X1
NOT COMPARED OA21XL OA21XL
NOT COMPARED OA22X1 OA22X1
NOT COMPARED OAI211X1 OAI211X1
NOT COMPARED OAI21X1 OAI21X1
NOT COMPARED OAI21XL OAI21XL
NOT COMPARED OAI221XL OAI221XL
NOT COMPARED OAI222XL OAI222XL
NOT COMPARED OAI22X1 OAI22X1
NOT COMPARED OAI22XL OAI22XL
INCORRECT OAI2BB1X1 OAI2BB1X1
NOT COMPARED OAI2BB2X1 OAI2BB2X1
NOT COMPARED OAI2BB2XL OAI2BB2XL
NOT COMPARED OAI31X1 OAI31X1
NOT COMPARED OAI31XL OAI31XL
NOT COMPARED OAI32XL OAI32XL
INCORRECT OR2X1 OR2X1
INCORRECT OR3X1 OR3X1
INCORRECT OR4X1 OR4X1
INCORRECT TIEHI TIEHI
INCORRECT TIELO TIELO
INCORRECT XNOR2X1 XNOR2X1
INCORRECT XOR2X1 XOR2X1
INCORRECT tag_initial tag
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
LVS COMPONENT TYPE PROPERTY element
LVS COMPONENT SUBTYPE PROPERTY model
LVS PIN NAME PROPERTY phy_pin
LVS POWER NAME "VDD" "vdd" "G" "D"
LVS GROUND NAME "VSS" "gnd" "S" "B"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES NO
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP NO
LVS ALL CAPACITOR PINS SWAPPABLE NO
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS FLATTEN INSIDE CELL NO
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS NO
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
// LVS SPICE EXCLUDE CELL SOURCE
// LVS SPICE EXCLUDE CELL LAYOUT
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS YES
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES YES
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LAYOUT CASE NO
SOURCE CASE NO
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM ALL
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// LVS IGNORE DEVICE PIN
// LVS PREFER NETS FILTER SOURCE
// LVS PREFER NETS FILTER LAYOUT
LVS PREFER PORT NETS NO
// Device Type Map
LVS DEVICE TYPE NMOS "nmos_5p0_dnw" SOURCE LAYOUT
LVS DEVICE TYPE NMOS "nmos_15p0_dnw" SOURCE LAYOUT
LVS DEVICE TYPE PMOS "pmos_5p0_dnw" SOURCE LAYOUT
LVS DEVICE TYPE PMOS "pmos_15p0_dnw" SOURCE LAYOUT
// Reduction
LVS REDUCE SERIES MOS YES
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS YES
LVS REDUCE SPLIT GATES NO
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCE M(bst) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE M(bst) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_1p5) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_1p5) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_1p5_lvt) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_1p5_lvt) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_1p5_nat) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_1p5_nat) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_1p5_sram) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_1p5_sram) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MP(pmos_1p5) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MP(pmos_1p5) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MP(pmos_1p5_lvt) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MP(pmos_1p5_lvt) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MP(pmos_1p5_sram) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MP(pmos_1p5_sram) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_3p3) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_3p3) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_3p3_nat) PARALLEL [ TOLERANCE L 0 ]
LVS REDUCE MN(nmos_3p3_nat) SERIES S D [ TOLERANCE L 0 M 0 ]
LVS REDUCE MP(pmos_3p3) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MP(pmos_3p3) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_15p0_nat) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_15p0_nat) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_15p0) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_15p0) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE nmos_15p0_dnw PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE nmos_15p0_dnw SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MP(pmos_15p0) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MP(pmos_15p0) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE pmos_15p0_dnw PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE pmos_15p0_dnw SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_16p0) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_16p0) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MP(pmos_16p0) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MP(pmos_16p0) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_5p0) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MN(nmos_5p0) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE nmos_5p0_dnw PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE nmos_5p0_dnw SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MP(pmos_5p0) PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE MP(pmos_5p0) SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE pmos_5p0_dnw PARALLEL [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE pmos_5p0_dnw SERIES S D [ TOLERANCE NF 0 L 0 W 0 ]
LVS REDUCE D(np_1p5) PARALLEL [ TOLERANCE A 0 P 0 ]
LVS REDUCE D(np_1p5_lvt) PARALLEL [ TOLERANCE A 0 P 0 ]
LVS REDUCE D(np_1p5_nat) PARALLEL [ TOLERANCE A 0 P 0 ]
LVS REDUCE D(pn_1p5) PARALLEL [ TOLERANCE A 0 P 0 ]
LVS REDUCE D(pn_1p5_lvt) PARALLEL [ TOLERANCE A 0 P 0 ]
LVS REDUCE D(np_3p3) PARALLEL [ TOLERANCE A 0 P 0 ]
LVS REDUCE D(np_3p3_nat) PARALLEL [ TOLERANCE A 0 P 0 ]
LVS REDUCE D(pn_3p3) PARALLEL [ TOLERANCE A 0 P 0 ]
LVS REDUCE D(pn_15p0) PARALLEL [ TOLERANCE A 0 P 0 ]
LVS REDUCE D(np_15p0) PARALLEL [ TOLERANCE A 0 P 0 ]
LVS REDUCE D(np_15p0_nat) PARALLEL [ TOLERANCE A 0 P 0 ]
LVS REDUCE D(nwp) PARALLEL [ TOLERANCE A 0 P 0 ]
LVS REDUCE D(dnwpw) PARALLEL [ TOLERANCE A 0 P 0 ]
LVS REDUCE D(dnwps) PARALLEL [ TOLERANCE A 0 P 0 ]
LVS REDUCE DNW PARALLEL [ TOLERANCE PW_AREA 0 PW_PERIM 0 DNW_AREA 0 DNW_PERIM 0 ]
LVS REDUCE D(zener_diode) PARALLEL
LVS REDUCE D(zener_diode_hv) PARALLEL
LVS REDUCE Q(vpnp_2x2) PARALLEL
LVS REDUCE Q(vpnp_5x5) PARALLEL
LVS REDUCE Q(vpnp_10x10) PARALLEL
LVS REDUCE Q(vnpn_hv_2x2) PARALLEL
LVS REDUCE R(nplus_s) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(nplus_s) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(pplus_s) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(pplus_s) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(nplus_u) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(nplus_u) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(pplus_u) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(pplus_u) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(npolyf_s) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(npolyf_s) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(ppolyf_s) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(ppolyf_s) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(npolyf_u) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(npolyf_u) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(ppolyf_u) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(ppolyf_u) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(ppolyf_u_1k) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(ppolyf_u_1k) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(nwell) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(nwell) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(rm1) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(rm1) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(rm2) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(rm2) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(rm3) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(rm3) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(rm4) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(rm4) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(rm5) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(rm5) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(rm6) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(rm6) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(rm7) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(rm7) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE R(tm9k) PARALLEL [ TOLERANCE L 0 W 0 ]
LVS REDUCE R(tm9k) SERIES POS NEG [ TOLERANCE L 0 W 0 M 0 ]
LVS REDUCE C(MIM_SM) PARALLEL [ TOLERANCE MIM_LENGTH 0 MIM_WIDTH 0 lm 0 ]
LVS REDUCE C(MIM_SM) SERIES POS NEG NO
LVS REDUCE C(mim_sm_bb) PARALLEL [ TOLERANCE MIM_LENGTH 0 MIM_WIDTH 0 ]
LVS REDUCE C(mim_sm_bb) SERIES POS NEG NO
LVS REDUCE RFNFET_1P5 PARALLEL [ TOLERANCE NFX 0 LX 0 WX 0 ]
LVS REDUCE RFNFET_1P5 SERIES S D NO
LVS REDUCE RFNFET_LVT_1P5 PARALLEL [ TOLERANCE NFX 0 LX 0 WX 0 ]
LVS REDUCE RFNFET_LVT_1P5 SERIES S D NO
LVS REDUCE RFPFET_1P5 PARALLEL [ TOLERANCE NFX 0 LX 0 WX 0 ]
LVS REDUCE RFPFET_1P5 SERIES S D NO
LVS REDUCE RFPFET_LVT_1P5 PARALLEL [ TOLERANCE NFX 0 LX 0 WX 0 ]
LVS REDUCE RFPFET_LVT_1P5 SERIES S D NO
LVS REDUCE RFNFET_3P3 PARALLEL [ TOLERANCE NFX 0 LX 0 WX 0 ]
LVS REDUCE RFNFET_3P3 SERIES S D NO
LVS REDUCE RFPFET_3P3 PARALLEL [ TOLERANCE NFX 0 LX 0 WX 0 ]
LVS REDUCE RFPFET_3P3 SERIES S D NO
LVS REDUCE NMOSVAR_1p5V_rf PARALLEL [ TOLERANCE F 0 LFinger 0 WFinger 0 ]
LVS REDUCE NMOSVAR_3p3V_rf PARALLEL [ TOLERANCE F 0 LFinger 0 WFinger 0 ]
LVS REDUCE PNVAR_1p5V_rf PARALLEL [ TOLERANCE F 0 LFinger 0 WFinger 0 ]
LVS REDUCE PNVAR_3p3V_rf PARALLEL [ TOLERANCE F 0 LFinger 0 WFinger 0 ]
LVS REDUCE C(pip_2p0ff) PARALLEL [ TOLERANCE l 0 w 0 ]
LVS REDUCE C(pip_2p0ff) SERIES POS NEG NO
LVS REDUCE pip_2p0ff_hvpwell PARALLEL [ TOLERANCE l 0 w 0 fet_l 0 fet_w 0 ]
LVS REDUCE pip_2p0ff_hvpwell SERIES PLUS MINUS NO
LVS REDUCE D(schd_hvnw_d8) PARALLEL NO
LVS REDUCE D(schd_hvnw_d8) SERIES POS NEG NO
LVS REDUCE D(schd_hvnw_d2) PARALLEL NO
LVS REDUCE D(schd_hvnw_d2) SERIES POS NEG NO
LVS REDUCTION PRIORITY PARALLEL
LVS SHORT EQUIVALENT NODES NO
// Trace Property
TRACE PROPERTY m(bst) m m 0
TRACE PROPERTY m(bst) nf nf 0
TRACE PROPERTY m(bst) l l 0
TRACE PROPERTY m(bst) w w 0
TRACE PROPERTY mn(nmos_1p5) m m 0
TRACE PROPERTY mn(nmos_1p5) nf nf 0
TRACE PROPERTY mn(nmos_1p5) l l 0
TRACE PROPERTY mn(nmos_1p5) w w 0
TRACE PROPERTY mn(nmos_1p5_lvt) m m 0
TRACE PROPERTY mn(nmos_1p5_lvt) nf nf 0
TRACE PROPERTY mn(nmos_1p5_lvt) l l 0
TRACE PROPERTY mn(nmos_1p5_lvt) w w 0
TRACE PROPERTY mn(nmos_1p5_nat) m m 0
TRACE PROPERTY mn(nmos_1p5_nat) nf nf 0
TRACE PROPERTY mn(nmos_1p5_nat) l l 0
TRACE PROPERTY mn(nmos_1p5_nat) w w 0
TRACE PROPERTY mn(nmos_1p5_sram) m m 0
TRACE PROPERTY mn(nmos_1p5_sram) nf nf 0
TRACE PROPERTY mn(nmos_1p5_sram) l l 0
TRACE PROPERTY mn(nmos_1p5_sram) w w 0
TRACE PROPERTY mp(pmos_1p5) m m 0
TRACE PROPERTY mp(pmos_1p5) nf nf 0
TRACE PROPERTY mp(pmos_1p5) l l 0
TRACE PROPERTY mp(pmos_1p5) w w 0
TRACE PROPERTY mp(pmos_1p5_lvt) m m 0
TRACE PROPERTY mp(pmos_1p5_lvt) nf nf 0
TRACE PROPERTY mp(pmos_1p5_lvt) l l 0
TRACE PROPERTY mp(pmos_1p5_lvt) w w 0
TRACE PROPERTY mp(pmos_1p5_sram) m m 0
TRACE PROPERTY mp(pmos_1p5_sram) nf nf 0
TRACE PROPERTY mp(pmos_1p5_sram) l l 0
TRACE PROPERTY mp(pmos_1p5_sram) w w 0
TRACE PROPERTY mn(nmos_3p3) m m 0
TRACE PROPERTY mn(nmos_3p3) nf nf 0
TRACE PROPERTY mn(nmos_3p3) l l 0
TRACE PROPERTY mn(nmos_3p3) w w 0
TRACE PROPERTY mn(nmos_3p3_nat) m m 0
TRACE PROPERTY mn(nmos_3p3_nat) l l 0
TRACE PROPERTY mn(nmos_3p3_nat) w w 0
TRACE PROPERTY mp(pmos_3p3) m m 0
TRACE PROPERTY mp(pmos_3p3) nf nf 0
TRACE PROPERTY mp(pmos_3p3) l l 0
TRACE PROPERTY mp(pmos_3p3) w w 0
TRACE PROPERTY mn(nmos_15p0_nat) m m 0
TRACE PROPERTY mn(nmos_15p0_nat) nf nf 0
TRACE PROPERTY mn(nmos_15p0_nat) l l 0
TRACE PROPERTY mn(nmos_15p0_nat) w w 0
TRACE PROPERTY mn(nmos_15p0) m m 0
TRACE PROPERTY mn(nmos_15p0) nf nf 0
TRACE PROPERTY mn(nmos_15p0) l l 0
TRACE PROPERTY mn(nmos_15p0) w w 0
TRACE PROPERTY nmos_15p0_dnw m m 0
TRACE PROPERTY nmos_15p0_dnw nf nf 0
TRACE PROPERTY nmos_15p0_dnw l l 0
TRACE PROPERTY nmos_15p0_dnw w w 0
TRACE PROPERTY mp(pmos_15p0) m m 0
TRACE PROPERTY mp(pmos_15p0) nf nf 0
TRACE PROPERTY mp(pmos_15p0) l l 0
TRACE PROPERTY mp(pmos_15p0) w w 0
TRACE PROPERTY pmos_15p0_dnw m m 0
TRACE PROPERTY pmos_15p0_dnw nf nf 0
TRACE PROPERTY pmos_15p0_dnw l l 0
TRACE PROPERTY pmos_15p0_dnw w w 0
TRACE PROPERTY mn(nmos_16p0) m m 0
TRACE PROPERTY mn(nmos_16p0) nf nf 0
TRACE PROPERTY mn(nmos_16p0) l l 0
TRACE PROPERTY mn(nmos_16p0) w w 0
TRACE PROPERTY mp(pmos_16p0) m m 0
TRACE PROPERTY mp(pmos_16p0) nf nf 0
TRACE PROPERTY mp(pmos_16p0) l l 0
TRACE PROPERTY mp(pmos_16p0) w w 0
TRACE PROPERTY mn(nmos_5p0) m m 0
TRACE PROPERTY mn(nmos_5p0) nf nf 0
TRACE PROPERTY mn(nmos_5p0) l l 0
TRACE PROPERTY mn(nmos_5p0) w w 0
TRACE PROPERTY nmos_5p0_dnw m m 0
TRACE PROPERTY nmos_5p0_dnw nf nf 0
TRACE PROPERTY nmos_5p0_dnw l l 0
TRACE PROPERTY nmos_5p0_dnw w w 0
TRACE PROPERTY mp(pmos_5p0) m m 0
TRACE PROPERTY mp(pmos_5p0) nf nf 0
TRACE PROPERTY mp(pmos_5p0) l l 0
TRACE PROPERTY mp(pmos_5p0) w w 0
TRACE PROPERTY pmos_5p0_dnw m m 0
TRACE PROPERTY pmos_5p0_dnw nf nf 0
TRACE PROPERTY pmos_5p0_dnw l l 0
TRACE PROPERTY pmos_5p0_dnw w w 0
TRACE PROPERTY d(np_1p5) m m 0
TRACE PROPERTY d(np_1p5) a a 1
TRACE PROPERTY d(np_1p5) p p 1
TRACE PROPERTY d(np_1p5_lvt) m m 0
TRACE PROPERTY d(np_1p5_lvt) a a 1
TRACE PROPERTY d(np_1p5_lvt) p p 1
TRACE PROPERTY d(np_1p5_nat) m m 0
TRACE PROPERTY d(np_1p5_nat) a a 1
TRACE PROPERTY d(np_1p5_nat) p p 1
TRACE PROPERTY d(pn_1p5) m m 0
TRACE PROPERTY d(pn_1p5) a a 1
TRACE PROPERTY d(pn_1p5) p p 1
TRACE PROPERTY d(pn_1p5_lvt) m m 0
TRACE PROPERTY d(pn_1p5_lvt) a a 1
TRACE PROPERTY d(pn_1p5_lvt) p p 1
TRACE PROPERTY d(np_3p3) m m 0
TRACE PROPERTY d(np_3p3) a a 1
TRACE PROPERTY d(np_3p3) p p 1
TRACE PROPERTY d(np_3p3_nat) m m 0
TRACE PROPERTY d(np_3p3_nat) a a 1
TRACE PROPERTY d(np_3p3_nat) p p 1
TRACE PROPERTY d(pn_3p3) m m 0
TRACE PROPERTY d(pn_3p3) a a 1
TRACE PROPERTY d(pn_3p3) p p 1
TRACE PROPERTY d(pn_15p0) m m 0
TRACE PROPERTY d(pn_15p0) a a 1
TRACE PROPERTY d(pn_15p0) p p 1
TRACE PROPERTY d(np_15p0) m m 0
TRACE PROPERTY d(np_15p0) a a 1
TRACE PROPERTY d(np_15p0) p p 1
TRACE PROPERTY d(np_15p0_nat) m m 0
TRACE PROPERTY d(np_15p0_nat) a a 1
TRACE PROPERTY d(np_15p0_nat) p p 1
TRACE PROPERTY d(nwp) m m 0
TRACE PROPERTY d(nwp) a a 1
TRACE PROPERTY d(nwp) p p 1
TRACE PROPERTY d(dnwpw) m m 0
TRACE PROPERTY d(dnwpw) a a 1
TRACE PROPERTY d(dnwpw) p p 1
TRACE PROPERTY d(dnwps) m m 0
TRACE PROPERTY d(dnwps) a a 1
TRACE PROPERTY d(dnwps) p p 1
TRACE PROPERTY dnw pw_area pw_area 1
TRACE PROPERTY dnw pw_perim pw_perim 1
TRACE PROPERTY dnw dnw_area dnw_area 1
TRACE PROPERTY dnw dnw_perim dnw_perim 1
TRACE PROPERTY d(zener_diode) m m 0
TRACE PROPERTY d(zener_diode_hv) m m 0
TRACE PROPERTY q(vpnp_2x2) m m 0
TRACE PROPERTY q(vpnp_5x5) m m 0
TRACE PROPERTY q(vpnp_10x10) m m 0
TRACE PROPERTY q(vnpn_hv_2x2) m m 0
TRACE PROPERTY r(nplus_s) m m 0
TRACE PROPERTY r(nplus_s) l l 0
TRACE PROPERTY r(nplus_s) w w 0
TRACE PROPERTY r(pplus_s) m m 0
TRACE PROPERTY r(pplus_s) l l 0
TRACE PROPERTY r(pplus_s) w w 0
TRACE PROPERTY r(nplus_u) m m 0
TRACE PROPERTY r(nplus_u) l l 0
TRACE PROPERTY r(nplus_u) w w 0
TRACE PROPERTY r(pplus_u) m m 0
TRACE PROPERTY r(pplus_u) l l 0
TRACE PROPERTY r(pplus_u) w w 0
TRACE PROPERTY r(npolyf_s) m m 0
TRACE PROPERTY r(npolyf_s) l l 0
TRACE PROPERTY r(npolyf_s) w w 0
TRACE PROPERTY r(ppolyf_s) m m 0
TRACE PROPERTY r(ppolyf_s) l l 0
TRACE PROPERTY r(ppolyf_s) w w 0
TRACE PROPERTY r(npolyf_u) m m 0
TRACE PROPERTY r(npolyf_u) l l 0
TRACE PROPERTY r(npolyf_u) w w 0
TRACE PROPERTY r(ppolyf_u) m m 0
TRACE PROPERTY r(ppolyf_u) l l 0
TRACE PROPERTY r(ppolyf_u) w w 0
TRACE PROPERTY r(ppolyf_u_1k) m m 0
TRACE PROPERTY r(ppolyf_u_1k) l l 0
TRACE PROPERTY r(ppolyf_u_1k) w w 0
TRACE PROPERTY r(nwell) m m 0
TRACE PROPERTY r(nwell) l l 0
TRACE PROPERTY r(nwell) w w 0
TRACE PROPERTY r(rm1) m m 0
TRACE PROPERTY r(rm1) l l 0
TRACE PROPERTY r(rm1) w w 0
TRACE PROPERTY r(rm2) m m 0
TRACE PROPERTY r(rm2) l l 0
TRACE PROPERTY r(rm2) w w 0
TRACE PROPERTY r(rm3) m m 0
TRACE PROPERTY r(rm3) l l 0
TRACE PROPERTY r(rm3) w w 0
TRACE PROPERTY r(rm4) m m 0
TRACE PROPERTY r(rm4) l l 0
TRACE PROPERTY r(rm4) w w 0
TRACE PROPERTY r(rm5) m m 0
TRACE PROPERTY r(rm5) l l 0
TRACE PROPERTY r(rm5) w w 0
TRACE PROPERTY r(rm6) m m 0
TRACE PROPERTY r(rm6) l l 0
TRACE PROPERTY r(rm6) w w 0
TRACE PROPERTY r(rm7) m m 0
TRACE PROPERTY r(rm7) l l 0
TRACE PROPERTY r(rm7) w w 0
TRACE PROPERTY r(tm9k) m m 0
TRACE PROPERTY r(tm9k) l l 0
TRACE PROPERTY r(tm9k) w w 0
TRACE PROPERTY c(mim_sm) m m 0
TRACE PROPERTY c(mim_sm) mim_length mim_length 0
TRACE PROPERTY c(mim_sm) mim_width mim_width 0
TRACE PROPERTY c(mim_sm) lm lm 0
TRACE PROPERTY c(mim_sm_bb) m m 0
TRACE PROPERTY c(mim_sm_bb) mim_length mim_length 0
TRACE PROPERTY c(mim_sm_bb) mim_width mim_width 0
TRACE PROPERTY c(pip_2p0ff) m m 0
TRACE PROPERTY c(pip_2p0ff) l l 0
TRACE PROPERTY c(pip_2p0ff) w w 0
TRACE PROPERTY pip_2p0ff_hvpwell finger finger 0
TRACE PROPERTY pip_2p0ff_hvpwell l l 0
TRACE PROPERTY pip_2p0ff_hvpwell w w 0
TRACE PROPERTY pip_2p0ff_hvpwell fet_l fet_l 0
TRACE PROPERTY pip_2p0ff_hvpwell fet_w fet_w 0
TRACE PROPERTY d(schd_hvnw_d8) m m 0
TRACE PROPERTY d(schd_hvnw_d2) m m 0
TRACE PROPERTY rfnfet_1p5 mx mx 0
TRACE PROPERTY rfnfet_1p5 nfx nfx 0
TRACE PROPERTY rfnfet_1p5 lx lx 0
TRACE PROPERTY rfnfet_1p5 wx wx 0
TRACE PROPERTY rfnfet_lvt_1p5 mx mx 0
TRACE PROPERTY rfnfet_lvt_1p5 nfx nfx 0
TRACE PROPERTY rfnfet_lvt_1p5 lx lx 0
TRACE PROPERTY rfnfet_lvt_1p5 wx wx 0
TRACE PROPERTY rfpfet_1p5 mx mx 0
TRACE PROPERTY rfpfet_1p5 nfx nfx 0
TRACE PROPERTY rfpfet_1p5 lx lx 0
TRACE PROPERTY rfpfet_1p5 wx wx 0
TRACE PROPERTY rfpfet_lvt_1p5 mx mx 0
TRACE PROPERTY rfpfet_lvt_1p5 nfx nfx 0
TRACE PROPERTY rfpfet_lvt_1p5 lx lx 0
TRACE PROPERTY rfpfet_lvt_1p5 wx wx 0
TRACE PROPERTY rfnfet_3p3 mx mx 0
TRACE PROPERTY rfnfet_3p3 nfx nfx 0
TRACE PROPERTY rfnfet_3p3 lx lx 0
TRACE PROPERTY rfnfet_3p3 wx wx 0
TRACE PROPERTY rfpfet_3p3 mx mx 0
TRACE PROPERTY rfpfet_3p3 nfx nfx 0
TRACE PROPERTY rfpfet_3p3 lx lx 0
TRACE PROPERTY rfpfet_3p3 wx wx 0
TRACE PROPERTY nmosvar_1p5v_rf mcell mcell 0
TRACE PROPERTY nmosvar_1p5v_rf f f 0
TRACE PROPERTY nmosvar_1p5v_rf lfinger lfinger 0
TRACE PROPERTY nmosvar_1p5v_rf wfinger wfinger 0
TRACE PROPERTY nmosvar_3p3v_rf mcell mcell 0
TRACE PROPERTY nmosvar_3p3v_rf f f 0
TRACE PROPERTY nmosvar_3p3v_rf lfinger lfinger 0
TRACE PROPERTY nmosvar_3p3v_rf wfinger wfinger 0
TRACE PROPERTY pnvar_1p5v_rf mcell mcell 0
TRACE PROPERTY pnvar_1p5v_rf f f 0
TRACE PROPERTY pnvar_1p5v_rf lfinger lfinger 0
TRACE PROPERTY pnvar_1p5v_rf wfinger wfinger 0
TRACE PROPERTY pnvar_3p3v_rf mcell mcell 0
TRACE PROPERTY pnvar_3p3v_rf f f 0
TRACE PROPERTY pnvar_3p3v_rf lfinger lfinger 0
TRACE PROPERTY pnvar_3p3v_rf wfinger wfinger 0
CELL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Properties missing on instances in source.
LAYOUT CELL NAME: ADDFXL
SOURCE CELL NAME: ADDFXL
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 15 7 *
Nets: 15 15
Instances: 14 14 MN (4 pins)
14 14 MP (4 pins)
------ ------
Total Inst: 28 28
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 7 7
Nets: 15 15
Instances: 1 1 MN (4 pins)
1 1 MP (4 pins)
1 1 _bitcoreb (6 pins)
1 1 _invb (6 pins)
6 6 _invv (4 pins)
2 2 _tgmb (7 pins)
------ ------
Total Inst: 12 12
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
SOURCE ERRORS
DISC#
**************************************************************************************************************
Properties Missing on Instances:
1 property nf not found on M27 (MN)
2 property nf not found on M26 (MP)
3 property nf not found on M25 (MN)
4 property nf not found on M24 (MP)
5 property nf not found on M23 (MN)
6 property nf not found on M22 (MP)
7 property nf not found on M21 (MN)
8 property nf not found on M20 (MP)
9 property nf not found on M19 (MN)
10 property nf not found on M18 (MP)
11 property nf not found on M17 (MN)
12 property nf not found on M16 (MP)
13 property nf not found on M15 (MN)
14 property nf not found on M14 (MN)
15 property nf not found on M13 (MN)
16 property nf not found on M12 (MN)
17 property nf not found on M11 (MN)
18 property nf not found on M10 (MN)
19 property nf not found on M9 (MN)
20 property nf not found on M8 (MN)
21 property nf not found on M7 (MP)
22 property nf not found on M6 (MP)
23 property nf not found on M5 (MP)
24 property nf not found on M4 (MP)
25 property nf not found on M3 (MP)
26 property nf not found on M2 (MP)
27 property nf not found on M1 (MP)
28 property nf not found on M0 (MP)
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 7 7 0 0
Nets: 15 15 0 0
Instances: 1 1 0 0 MN(NMOS_1P5)
1 1 0 0 MP(PMOS_1P5)
1 1 0 0 _bitcoreb
1 1 0 0 _invb
6 6 0 0 _invv
2 2 0 0 _tgmb
------- ------- --------- ---------
Total Inst: 12 12 0 0
o Statistics:
28 source properties were missing.
8 layout trivial ports were deleted.
CELL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Properties missing on instances in source.
LAYOUT CELL NAME: ADDHXL
SOURCE CELL NAME: ADDHXL
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 10 6 *
Nets: 11 11
Instances: 8 8 MN (4 pins)
8 8 MP (4 pins)
------ ------
Total Inst: 16 16
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 6 6
Nets: 8 8
Instances: 2 2 _invv (4 pins)
1 1 _nand2v (5 pins)
1 1 _xra2v (5 pins)
------ ------
Total Inst: 4 4
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
SOURCE ERRORS
DISC#
**************************************************************************************************************
Properties Missing on Instances:
1 property nf not found on M15 (MN)
2 property nf not found on M14 (MP)
3 property nf not found on M13 (MN)
4 property nf not found on M12 (MP)
5 property nf not found on M11 (MN)
6 property nf not found on M10 (MP)
7 property nf not found on M9 (MN)
8 property nf not found on M8 (MP)
9 property nf not found on M7 (MN)
10 property nf not found on M6 (MN)
11 property nf not found on M5 (MP)
12 property nf not found on M4 (MP)
13 property nf not found on M3 (MP)
14 property nf not found on M2 (MP)
15 property nf not found on M1 (MN)
16 property nf not found on M0 (MN)
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 6 6 0 0
Nets: 8 8 0 0
Instances: 2 2 0 0 _invv
1 1 0 0 _nand2v
1 1 0 0 _xra2v
------- ------- --------- ---------
Total Inst: 4 4 0 0
o Statistics:
16 source properties were missing.
4 layout trivial ports were deleted.
CELL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Properties missing on instances in source.
LAYOUT CELL NAME: XOR2X1
SOURCE CELL NAME: XOR2X1
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 8 5 *
Nets: 8 8
Instances: 5 5 MN (4 pins)
5 5 MP (4 pins)
------ ------
Total Inst: 10 10
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 5 5
Nets: 6 6
Instances: 1 1 _invv (4 pins)
1 1 _xra2v (5 pins)
------ ------
Total Inst: 2 2
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
SOURCE ERRORS
DISC#
**************************************************************************************************************
Properties Missing on Instances:
1 property nf not found on M9 (MN)
2 property nf not found on M8 (MP)
3 property nf not found on M7 (MN)
4 property nf not found on M6 (MP)
5 property nf not found on M5 (MN)
6 property nf not found on M4 (MP)
7 property nf not found on M3 (MN)
8 property nf not found on M2 (MN)
9 property nf not found on M1 (MP)
10 property nf not found on M0 (MP)
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 5 5 0 0
Nets: 6 6 0 0
Instances: 1 1 0 0 _invv
1 1 0 0 _xra2v
------- ------- --------- ---------
Total Inst: 2 2 0 0
o Statistics:
10 source properties were missing.
3 layout trivial ports were deleted.
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of ports (see below).
Error: Connectivity errors.
Error: Cells with non-floating extra pins.
Warning: Ambiguity points were found and resolved arbitrarily.
LAYOUT CELL NAME: tag_initial
SOURCE CELL NAME: tag
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 0 38 *
Nets: 12087 4858 *
Instances: 27 27 ADDFXL (7 pins)
68 68 ADDHXL (6 pins)
22 22 AND2X1 (5 pins)
1 1 AND3X1 (6 pins)
2 2 AND4X1 (7 pins)
20 20 AO21X1 (0 pins)
105 105 AO22X1 (0 pins)
2 2 AOI211X1 (0 pins)
181 181 AOI211XL (0 pins)
31 31 AOI21XL (0 pins)
2 2 AOI221X1 (0 pins)
53 53 AOI221XL (0 pins)
30 30 AOI222XL (0 pins)
42 42 AOI22XL (0 pins)
28 28 AOI2BB1X1 (6 pins)
136 136 AOI2BB2X1 (0 pins)
1 1 AOI31X1 (0 pins)
12 12 AOI31XL (0 pins)
3 3 AOI32XL (0 pins)
2 2 AOI33XL (0 pins)
4 4 CLKBUFX2 (1 pins)
1 1 CLKBUFX20 (0 pins)
1 1 CLKBUFX3 (4 pins)
1 1 CLKBUFX4 (3 pins)
29 29 CLKBUFX6 (1 pins)
6 6 CLKINVX1 (4 pins)
3 3 CLKINVX12 (0 pins)
1 1 CLKINVX16 (0 pins)
2 2 CLKINVX2 (4 pins)
1 1 CLKINVX3 (4 pins)
61 61 CLKINVX4 (4 pins)
7 7 CLKINVX6 (0 pins)
6 6 CLKINVX8 (0 pins)
2 2 DFFHQX8 (5 pins)
1 1 DFFNSRX1 (7 pins)
653 653 DFFQX1 (5 pins)
22 22 DFFRX1 (7 pins)
2 2 EDFFX1 (6 pins)
644 644 INVX1 (4 pins)
1 1 INVX3 (4 pins)
3 3 MXI2X1 (6 pins)
27 27 NAND2BX1 (5 pins)
362 362 NAND2X1 (5 pins)
2 2 NAND2X2 (5 pins)
14 14 NAND3BX1 (6 pins)
67 67 NAND3X1 (6 pins)
1 1 NAND3X2 (6 pins)
1 1 NAND4BBXL (7 pins)
4 4 NAND4BX1 (7 pins)
46 46 NAND4X1 (7 pins)
4 4 NOR2BX1 (5 pins)
48 48 NOR2BXL (5 pins)
361 361 NOR2X1 (5 pins)
5 5 NOR2X2 (5 pins)
8 8 NOR3BXL (6 pins)
2 2 NOR3X1 (6 pins)
1 1 NOR3X2 (6 pins)
53 53 NOR3XL (6 pins)
4 4 NOR4BXL (7 pins)
5 5 NOR4X1 (7 pins)
62 62 NOR4XL (7 pins)
7 7 OA21X1 (0 pins)
5 5 OA21XL (0 pins)
53 53 OA22X1 (0 pins)
110 110 OAI211X1 (0 pins)
147 147 OAI21X1 (0 pins)
358 358 OAI21XL (0 pins)
5 5 OAI221XL (0 pins)
12 12 OAI222XL (0 pins)
2 2 OAI22X1 (0 pins)
408 408 OAI22XL (0 pins)
20 20 OAI2BB1X1 (6 pins)
2 2 OAI2BB2X1 (0 pins)
98 98 OAI2BB2XL (0 pins)
1 1 OAI31X1 (0 pins)
91 91 OAI31XL (0 pins)
9 9 OAI32XL (0 pins)
14 14 OR2X1 (5 pins)
1 1 OR3X1 (6 pins)
4 4 OR4X1 (7 pins)
1 1 TIEHI (3 pins)
1 1 TIELO (2 pins)
13 13 XNOR2X1 (5 pins)
12 12 XOR2X1 (5 pins)
------ ------
Total Inst: 4670 4670
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 0 15 *
Nets: 3846 3846
Instances: 27 27 ADDFXL (7 pins)
68 68 ADDHXL (6 pins)
22 22 AND2X1 (5 pins)
1 1 AND3X1 (6 pins)
2 2 AND4X1 (7 pins)
20 20 AO21X1 (0 pins)
105 105 AO22X1 (0 pins)
2 2 AOI211X1 (0 pins)
181 181 AOI211XL (0 pins)
31 31 AOI21XL (0 pins)
2 2 AOI221X1 (0 pins)
53 53 AOI221XL (0 pins)
30 30 AOI222XL (0 pins)
42 42 AOI22XL (0 pins)
28 28 AOI2BB1X1 (6 pins)
136 136 AOI2BB2X1 (0 pins)
1 1 AOI31X1 (0 pins)
12 12 AOI31XL (0 pins)
3 3 AOI32XL (0 pins)
2 2 AOI33XL (0 pins)
4 4 CLKBUFX2 (1 pins)
1 1 CLKBUFX20 (0 pins)
1 1 CLKBUFX3 (4 pins)
1 1 CLKBUFX4 (3 pins)
29 29 CLKBUFX6 (1 pins)
6 6 CLKINVX1 (4 pins)
3 3 CLKINVX12 (0 pins)
1 1 CLKINVX16 (0 pins)
2 2 CLKINVX2 (4 pins)
1 1 CLKINVX3 (4 pins)
61 61 CLKINVX4 (4 pins)
7 7 CLKINVX6 (0 pins)
6 6 CLKINVX8 (0 pins)
2 2 DFFHQX8 (5 pins)
1 1 DFFNSRX1 (7 pins)
653 653 DFFQX1 (5 pins)
22 22 DFFRX1 (7 pins)
2 2 EDFFX1 (6 pins)
644 644 INVX1 (4 pins)
1 1 INVX3 (4 pins)
3 3 MXI2X1 (6 pins)
27 27 NAND2BX1 (5 pins)
362 362 NAND2X1 (5 pins)
2 2 NAND2X2 (5 pins)
14 14 NAND3BX1 (6 pins)
67 67 NAND3X1 (6 pins)
1 1 NAND3X2 (6 pins)
1 1 NAND4BBXL (7 pins)
4 4 NAND4BX1 (7 pins)
46 46 NAND4X1 (7 pins)
4 4 NOR2BX1 (5 pins)
48 48 NOR2BXL (5 pins)
361 361 NOR2X1 (5 pins)
5 5 NOR2X2 (5 pins)
8 8 NOR3BXL (6 pins)
2 2 NOR3X1 (6 pins)
1 1 NOR3X2 (6 pins)
53 53 NOR3XL (6 pins)
4 4 NOR4BXL (7 pins)
5 5 NOR4X1 (7 pins)
62 62 NOR4XL (7 pins)
7 7 OA21X1 (0 pins)
5 5 OA21XL (0 pins)
53 53 OA22X1 (0 pins)
110 110 OAI211X1 (0 pins)
147 147 OAI21X1 (0 pins)
358 358 OAI21XL (0 pins)
5 5 OAI221XL (0 pins)
12 12 OAI222XL (0 pins)
2 2 OAI22X1 (0 pins)
408 408 OAI22XL (0 pins)
20 20 OAI2BB1X1 (6 pins)
2 2 OAI2BB2X1 (0 pins)
98 98 OAI2BB2XL (0 pins)
1 1 OAI31X1 (0 pins)
91 91 OAI31XL (0 pins)
9 9 OAI32XL (0 pins)
14 14 OR2X1 (5 pins)
1 1 OR3X1 (6 pins)
4 4 OR4X1 (7 pins)
1 1 TIEHI (3 pins)
1 1 TIELO (2 pins)
13 13 XNOR2X1 (5 pins)
12 12 XOR2X1 (5 pins)
------ ------
Total Inst: 4670 4670
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 Net 1 ** no similar net **
--------------------------------------------------------------------------------------------------------------
2 Net 2 ** no similar net **
--------------------------------------------------------------------------------------------------------------
3 ** no similar net ** VDD
--------------------------------------------------------------------------------------------------------------
4 ** no similar net ** VSS
**************************************************************************************************************
INCORRECT PORTS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
5 ** missing port ** VDD on net: VDD
6 ** missing port ** VSS on net: VSS
7 ** missing port ** RST on net: RST
8 ** missing port ** CLK on net: CLK
9 ** missing port ** SEED on net: SEED
10 ** missing port ** CLK_CONTROL_1 on net: CLK_CONTROL_1
11 ** missing port ** CLK_CONTROL_0 on net: CLK_CONTROL_0
12 ** missing port ** DATAFROMEE on net: DATAFROMEE
13 ** missing port ** PROG on net: PROG
14 ** missing port ** ADDRESS_4 on net: ADDRESS_4
15 ** missing port ** ADDRESS_2 on net: ADDRESS_2
16 ** missing port ** ADDRESS_1 on net: ADDRESS_1
17 ** missing port ** ADDRESS_0 on net: ADDRESS_0
18 ** missing port ** RECEIVE on net: RECEIVE
19 ** missing port ** EW on net: EW
**************************************************************************************************************
INSTANCES OF CELLS WITH NON-FLOATING EXTRA PINS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
20 X0/X626(118.910,181.495) CLKBUFX4 XU1 CLKBUFX4
** missing pin ** X0/X626/4 XU1/A ATA
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 0 0 0 15
Nets: 3844 3844 2 2
Instances: 27 27 0 0 ADDFXL
68 68 0 0 ADDHXL
22 22 0 0 AND2X1
1 1 0 0 AND3X1
2 2 0 0 AND4X1
20 20 0 0 AO21X1
105 105 0 0 AO22X1
2 2 0 0 AOI211X1
181 181 0 0 AOI211XL
31 31 0 0 AOI21XL
2 2 0 0 AOI221X1
53 53 0 0 AOI221XL
30 30 0 0 AOI222XL
42 42 0 0 AOI22XL
28 28 0 0 AOI2BB1X1
136 136 0 0 AOI2BB2X1
1 1 0 0 AOI31X1
12 12 0 0 AOI31XL
3 3 0 0 AOI32XL
2 2 0 0 AOI33XL
4 4 0 0 CLKBUFX2
1 1 0 0 CLKBUFX20
1 1 0 0 CLKBUFX3
1 1 0 0 CLKBUFX4
29 29 0 0 CLKBUFX6
6 6 0 0 CLKINVX1
3 3 0 0 CLKINVX12
1 1 0 0 CLKINVX16
2 2 0 0 CLKINVX2
1 1 0 0 CLKINVX3
61 61 0 0 CLKINVX4
7 7 0 0 CLKINVX6
6 6 0 0 CLKINVX8
2 2 0 0 DFFHQX8
1 1 0 0 DFFNSRX1
653 653 0 0 DFFQX1
22 22 0 0 DFFRX1
2 2 0 0 EDFFX1
644 644 0 0 INVX1
1 1 0 0 INVX3
3 3 0 0 MXI2X1
27 27 0 0 NAND2BX1
362 362 0 0 NAND2X1
2 2 0 0 NAND2X2
14 14 0 0 NAND3BX1
67 67 0 0 NAND3X1
1 1 0 0 NAND3X2
1 1 0 0 NAND4BBXL
4 4 0 0 NAND4BX1
46 46 0 0 NAND4X1
4 4 0 0 NOR2BX1
48 48 0 0 NOR2BXL
361 361 0 0 NOR2X1
5 5 0 0 NOR2X2
8 8 0 0 NOR3BXL
2 2 0 0 NOR3X1
1 1 0 0 NOR3X2
53 53 0 0 NOR3XL
4 4 0 0 NOR4BXL
5 5 0 0 NOR4X1
62 62 0 0 NOR4XL
7 7 0 0 OA21X1
5 5 0 0 OA21XL
53 53 0 0 OA22X1
110 110 0 0 OAI211X1
147 147 0 0 OAI21X1
358 358 0 0 OAI21XL
5 5 0 0 OAI221XL
12 12 0 0 OAI222XL
2 2 0 0 OAI22X1
408 408 0 0 OAI22XL
20 20 0 0 OAI2BB1X1
2 2 0 0 OAI2BB2X1
98 98 0 0 OAI2BB2XL
1 1 0 0 OAI31X1
91 91 0 0 OAI31XL
9 9 0 0 OAI32XL
14 14 0 0 OR2X1
1 1 0 0 OR3X1
4 4 0 0 OR4X1
1 1 0 0 TIEHI
1 1 0 0 TIELO
13 13 0 0 XNOR2X1
12 12 0 0 XOR2X1
------- ------- --------- ---------
Total Inst: 4670 4670 0 0
o Statistics:
8241 layout nets had all their pins removed and were deleted.
967 source nets had all their pins removed and were deleted.
23 source nets were reduced to passthrough nets and deleted.
404 nets and 53 instances were matched arbitrarily.
o Ambiguity Resolution Points:
(Each one of the following objects belongs to a group of indistinguishable objects.
The listed objects were matched arbitrarily by the Ambiguity Resolution feature of LVS.
Arbitrary matching may be prevented by assigning names to these objects or to adjacent nets).
Layout Source
------ ------
Nets
----
X5/920 n4587
X5/913 n4569
X4/888 n6695
1375 n6668
X4/885 n6678
X4/868 n6692
X4/875 n6685
X4/850 n6704
X4/842 n6712
X4/831 n6681
X4/822 n6689
X4/814 n6707
X4/800 n6675
1069 n6672
X4/781 n6669
X3/779 Xsub_x_76/n57
X3/742 n6698
X3/732 n6662
X0/731 encode_dout_fm0
1003 random_rnpre[15]
X7/443 n6309
X5/845 n4155
X6/595 n4244
X5/830 n4158
X6/626 n6027
839 n6025
X5/619 in[52]
X5/641 n3979
X5/946 kill_pwd[13]
X5/947 n6190
X3/754 n6701
1317 n6444
336 n6170
X3/565 memory_control_tempee[4]
X2/643 n5230
1209 location_new[0]
X1/784 clock_divider_encode_div_count[3]
1464 n4028
X5/820 n4086
X5/951 n4602
1323 n3688
X2/881 n4742
X2/541 n6507
35 n5404
258 n4377
X0/777 n5503
X2/553 CRC_3[13]
X2/868 n4753
X3/880 CRC_1[13]
613 trcal[2]
Instances
---------
X2/X660(195.730,111.450) AOI211X1 XU5699 AOI211X1
X4/X698(118.450,74.550) AOI221X1 XU7196 AOI221X1
X1/X639(257.370,148.350) AOI33XL XU7228 AOI33XL
X1/X648(58.190,137.215) OAI22X1 XU4940 OAI22X1
X0/X640(76.130,163.110) OAI2BB2X1 XU4787 OAI2BB2X1
X0/X660(9.430,159.355) CLKINVX12 XCLKINVX4_G3B1I2_4 CLKINVX12
X2/X652(16.790,133.590) CLKINVX12 XCLKINVX4_G3B1I1_4 CLKINVX12
X2/X659(203.090,115.075) AOI32XL XU7053 AOI32XL
X3/X596(193.890,96.690) AOI32XL XU5607 AOI32XL
X1/X650(16.330,144.595) OA21XL XU6080 OA21XL
X1/X651(58.190,148.350) OA21XL XU4827 OA21XL
X2/X656(218.270,129.835) OA21XL XU6826 OA21XL
X3/X595(143.750,92.935) OA21XL XU5963 OA21XL
X1/X643(231.150,137.215) OAI221XL XU6211 OAI221XL
X2/X654(228.390,122.455) OAI221XL XU5797 OAI221XL
X3/X593(126.270,104.070) OAI221XL XU5552 OAI221XL
X6/X589(254.610,33.895) OAI221XL XU5563 OAI221XL
X0/X563(194.350,163.110) CLKINVX8 XCLKINVX8_G1B2I1 CLKINVX8
X2/X616(71.070,133.590) CLKINVX8 XCLKINVX4_G3B1I1_5 CLKINVX8
X2/X617(100.510,126.210) CLKINVX8 XCLKINVX4_G3B1I4_3 CLKINVX8
X3/X560(14.030,104.070) CLKINVX8 XCLKINVX8_G1B2I2 CLKINVX8
X3/X561(226.550,100.315) CLKINVX8 XCLKINVX4_G3B2I1_1 CLKINVX8
X0/X552(179.630,181.495) CLKINVX6 XCLKINVX4_G3B1I4_1 CLKINVX6
X0/X553(213.210,170.490) CLKINVX6 XCLKINVX12_G1B5I1 CLKINVX6
X1/X588(68.310,155.730) CLKINVX6 XCLKINVX4_G3B2I1_3 CLKINVX6
X1/X589(108.330,155.730) CLKINVX6 XCLKINVX4_G3B2I1_5 CLKINVX6
X2/X603(77.510,129.835) CLKINVX6 XCLKINVX4_G3B2I1_2 CLKINVX6
X4/X575(187.910,81.930) CLKINVX6 XCLKINVX6_G1B2I3 CLKINVX6
X0/X641(42.550,174.115) OA21X1 XU7213 OA21X1
X0/X642(70.610,166.735) OA21X1 XU6233 OA21X1
X1/X632(227.470,137.215) OA21X1 XU6242 OA21X1
X2/X648(86.710,122.455) OA21X1 XU6006 OA21X1
X2/X649(157.090,111.450) OA21X1 XU5569 OA21X1
X4/X679(231.150,63.415) OA21X1 XU5393 OA21X1
X1/X644(225.170,148.350) OAI32XL XU6808 OAI32XL
X2/X655(259.210,129.835) OAI32XL XU6708 OAI32XL
X3/X594(190.670,104.070) OAI32XL XU6756 OAI32XL
X4/X685(233.910,78.175) OAI32XL XU6252 OAI32XL
X4/X686(239.890,78.175) OAI32XL XU5568 OAI32XL
X4/X687(243.110,70.795) OAI32XL XU4873 OAI32XL
X5/X584(246.790,48.655) OAI32XL XU4581 OAI32XL
X6/X590(118.450,30.270) OAI32XL XU3953 OAI32XL
X2/X663(96.830,118.830) OAI222XL XU7157 OAI222XL
X2/X664(111.090,115.075) OAI222XL XU7161 OAI222XL
X3/X597(191.590,92.935) OAI222XL XU6807 OAI222XL
X4/X689(134.090,85.555) OAI222XL XU5540 OAI222XL
X5/X587(98.670,45.030) OAI222XL XU4363 OAI222XL
X5/X588(98.670,48.655) OAI222XL XU4366 OAI222XL
X5/X589(100.510,41.275) OAI222XL XU4386 OAI222XL
X5/X590(114.770,41.275) OAI222XL XU4413 OAI222XL
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time: 0 sec
Total Elapsed Time: 0 sec
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