ISSCC2025 Paper 分Session整理

孤岛巨象

ISSCC2025 Paper 分Session整理如下，可按需下载，论文集可以下载 ISSCC2025-Digest：ISSCC2025-Digest - Analog/RF IC 资料共享 - EETOP 创芯网论坛 (原名：电子顶级开发网) -
Session 1: Plenary
        1.1 AI Era Innovation Matrix
        1.2 From Chips to Thoughts: Building Physical Intelligence into Robotic Systems
        1.3 AI Revolution Driven by Memory Technology Innovation
        1.4 The Crucial Role of Semiconductors in the Software-Defined Vehicle
Session 2: Processors
        2.1 “Zen 5”: The AMD High-Performance 4nm x86-64 Microprocessor Core
        2.2 IBM Telum II: Next Generation 5.5GHz Microprocessor with On-Die Data Processing Unit and Improved AI Accelerator
        2.3 Granite Rapids-D: Intel Xeon 6 SoC for vRAN, Edge, Networking, and Storage
        2.4 A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Wo
        2.5 A 16nm 5.7TOPS CNN Processor Supporting Bi-Directional FPN for Small-Object Detection on High-Resolution Videos
        2.6 1.78mJ/Frame 373fps 3D GS Processor Based on Shape-Aware Hybrid Architecture Using Earlier Computation Skipping and Gaussian
        2.7 IRIS: A 8.55mJ/frame Spatial Computing SoC for Interactable Rendering and Surface-Aware Modeling with 3D Gaussian Splatting
        2.8 A 210fps Image Signal Processor for 4K Ultra HD True Video Super Resolution
        2.9 STEP: An 8K-60fps Space-Time Resolution-Enhancement Neural-Network Processor for Next-Generation Display and Streaming
        2.10 A 0.52mJ/Frame 107fps Super-Resolution Processor Exploiting Pseudo-FP6 Sparsity for Mobile Applications
Session 3: Amplifiers and Analog Front-Ends
        3.1 A 121.3dB-DR, 115dB-PSNR, Digital-Input Capacitive-Feedback Class-D Audio Amplifier with Double-Sided Voltage-Boosting (DSVB
        3.2 A 36V Current-Balancing Instrumentation Amplifier with ±24V Input Range, 5.6MHz BW, and 140dB CMRR at All Gain Settings
        3.3 A Passive Switched-Capacitor-Based Multimode Amplifier with a Logarithmic Conformity Error of 0.75% from -25 to 200°C
        3.4 A CMOS Operational Amplifier Achieving ±5.8μV 3σ Offset and ±88nV/°C 3σ Offset Drift Using an On-Chip Heater-Based Self-Trim
Session 4: Analog Techniques
        4.1 A 12.8GS/s Sub-Sampling ADC Front-End with 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI
        4.2 A 1.8-to-3.0GHz Fully Integrated All-In-One CMOS Frequency Management Module Achieving -47/+42ppm Inaccuracy from -40 to 95°
        4.3 A 0.36nW, 820μm2, 32kHz Conduction-Angle-Adaptive Crystal Oscillator in 28nm CMOS for Real-Time Clock Applications
        4.4 A 0.36nW/0.9V 32kHz Crystal Oscillator Using Analog Regulation for Cross-Current Avoidance
        4.5 A 0.4μW/MHz Reference-Replication-Based RC Oscillator with Path-Delay and Comparator-Offset Cancellation Achieving 9.83ppm/°
        4.6 A 0.8V, 31ppm/°C, -40dB DC-to-GHz Power-Supply-Rejection Standard-Vth Core-MOS-Only Voltage Reference with a 294μm2 Area
Session 5: Front-End Circuits for High-Performance Transceivers
        5.1 A GaN SLCG-Doherty-Continuum Power Amplifier Achieving >38% 6dB Back-Off Efficiency over 1.35 to 7.6GHz
        5.2 Spatial-Temporal Direct-Digital Beamforming Power Amplifier with Enhanced Back-Off Efficiency in a 24GHz Phased Array
        5.3 A 56-to-64GHz Linear Power Amplifier with 30.2dBm Psat and 23.5% PAEpeak Using Scalable Matched-Zone-Expanding Radial Power
        5.4 A 22nm FDSOI CMOS-Based Compact 3-Stack Doherty Power Amplifier with a Stacked OPA-Based Bias Scheme Achieving >16.5dBm Pavg
        5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1-VSWR-Resilient Operations
        5.6 A Power-Efficient CORDIC-less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM
        5.7 A 4.7GHz, 27.7dBm Pout, 37.8% PAE, 5.8° AM-PM Distortion Polar SCPA Using In-Cell Fast Slope-to-Phase Self-Calibration and A
        5.8 A 20W CMOS/LDMOS All-Digital Transmitter with Dynamic Retiming and Glitch-Free Phase Mapper, Achieving 68%/62% Peak Drain/Sy
        5.9 A 21-to-31GHz DPD-less Quadrature RFDAC with Invariant Impedance and Scalable LO Leakage
        5.10 A 3.5mW mm-Wave Low-Noise Active Bandpass Filter Employing an All-Passive Interferer-Cancellation Feedforward Path
        5.11 A Blocker-Tolerant mm-Wave Low-Noise Amplifier Utilizing Doherty Active Load Modulation for Linearity Enhancement
Session 6: Imagers and Displays
        6.1 A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2μm-Pitch 50Mpixel Rolling Shutter and 2.4μm-Pitch 12.5Mpixel
        6.2 An Asynchronous 160×90 Flash LiDAR Sensor with Dynamic Frame Rates of 5 to 250fps Based on Pixelwise ToF Validation via a Ba
        6.3 SPAD Flash LiDAR with Chopped Analog Counter for 76m Range and 120klx Background Light
        6.4 A 400×400 3.24μm 117dB-Dynamic-Range 3-Layer Stacked Digital Pixel Sensor
        6.5 A 25.2Mpixel 120frames/s Full-Frame Global-Shutter CMOS Image Sensor with Pixel-Parallel ADC
        6.7 A 10b Source-Driver IC with All-Channel Automatic Offset Calibration and Slew-Rate-Enhanced Amplifier Achieving 2273μm2/Chan
        6.8 A Real-Time Pixel-Compensated Source-Driver IC with Dual-Slope Error Detection and Multi-Channel Time-Multiplexing Compensat
        6.9 A Compact 10b Source Driver IC with Delta-Sigma Pulse Width Modulation for Low-Voltage Digital Interpolation Achieving 1884μ
        6.10 A 10.5mW Automotive Touch AFE IC Featuring Radiated EMI Reduction Based on Pipelined Dual-Frequency Modulation and Sine2 Wa
Session 7: Ultra-High-Speed Wireline
        7.1 A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET
        7.2 A 2.2pJ/b 212.5Gb/s PAM-4 Transceiver with >46dB Reach in 5nm FinFET
        7.3 A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS
        7.4 A 112Gb/s DSP-Based PAM-4 Receiver with an LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm FinFET
        7.5 A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET
        7.6 A 2.06pJ/b 106.25Gb/s PAM-4 Receiver with 3-Tap FFE and 1-Tap Speculative DFE in 28nm CMOS
        7.7 A 50Gb/s Burst-Mode NRZ Receiver with 5-Tap FFE, 7-Tap DFE and 15ns Lock Time in 28nm CMOS for Symmetric 50G-PON
        7.8 A Reference-less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 6
        7.10 An 8-to-28GHz 8-Phase Clock Generator Using Dual-Feedback Ring Oscillator in 28nm CMOS
Session 8: Digital Techniques for System Adaptation, Power Management and Clocking
        8.1 Dynamic Guard-Band Features of the IBM zNext System
        8.2 Run-Time Power Management System by On-Die Power Sensor with Silicon Machine Learning-Based Calibration in a 3nm Octa-Core C
        8.3 A Dynamically Reconfigurable Digital-Integrated Voltage-Regulator Fabric for Energy-Efficient DVFS in Multi-Domain SoCs
        8.4 A 4GHz, 0.69%-Accuracy Voltage-Droop Detector with Multiple Remote Sensing and Under 2-Cycle Detection Latency in 2nm GAAFET
        8.5 A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150μA Quiescent Current and 20pF On-Chip Capacitor Achieving Sub
        8.6 A 0.024mm2 All-Digital Fractional Output Divider with 257fs Worst-Case Jitter Using Split-DTC-Based Background Calibration
        8.7 A Dual VDD-Temperature Sensor Employing Sensor Fusion with 2.4°C, 9mV (±3σ) Inaccuracy in 65nm CMOS
        8.8 Fine-Grained Spatial and Temporal Thermal Profiling of a 16nm CMOS Buck Converter and SoC Load-Current Emulator Using Low-Vo
        8.9 An On-Cell Monitoring and Balancing System With Near-Field Communications for EV Batteries
Session 9: Ubiquitous Power Delivery
        9.1 An 85-to-230VAC to 3.3-to-4.6VDC 1.52W Capacitor-Drop Sigma-Floating-SC AC-DC Converter with 81.3% Peak Efficiency
        9.2 A 400MHz Symbol-Power-Tracking (SPT) Supply Modulator with SPT-Adaptive-Biasing Network Supporting 5G FR2 CMOS PA
        9.3 A 74W/48V Monolithic-GaN Integrated Adjustable Multilevel Supply Modulator for 5G Base-Station Massive-MIMO Arrays
        9.4 A 102ns/V 94.3%-Peak-Efficiency Symbol-Power-Tracking Supply Modulator for 5G NR Power Amplifiers
        9.5 A Sub-1V, 50mV Dropout LDO Using Pseudo-Impedance Buffer with Phase-Margin Improvement Design
        9.6 A 6.78MHz Single-Stage Regulating Rectifier with Dual Outputs Simultaneously Charged in a Half Cycle Achieving 92.2% Efficie
        9.7 A 6.78MHz 94.2% Peak Efficiency Class-E Transmitter with Adaptive Real-Part Impedance Matching and Imaginary-Part Phase Comp
        9.8 A 50W 98%-Efficiency High-Power Wireless-Charging System with an Acoustic Noise-Reduced ASK Modulation Technique and Interna
        9.9 A Bi-Directional Dual-Path Boost-48V-Buck Hybrid Converter for High-Voltage Power-Transmission Cable in Light-Weight Humanoi
        9.10 A 93%-Peak-Efficiency Battery-Input 12-to-36V-Output Inductor-in-the-Middle Hybrid Boost Converter with Continuous Input an
        9.11 A 98.3%-Peak-Efficiency Single-Mode Hybrid Buck-Boost Converter with 7mV Maximum Output Ripple for Li-Ion Battery Managemen
Session 10: Transceiver Chipsets for Communications and Radar
        10.1 A 77GHz Hybrid TDMA-MIMO Phased-Array Radar with 186m Detection Range and 3cm Range Resolution
        10.2 A 132-to-148GHz CMOS 4TX-4RX FMCW Radar Transceiver Array with Cavity-Backed Antenna-in-Package Achieving 28dBm EIRP
        10.3 A D-Band 2D-Scalable 4×4 Active Reflective Relay with Orthogonally Polarized On-Chip TX/RX Antennas and In-Front-End Common
        10.4 A 2-TRX IR-UWB Transceiver with Shared Antennas Supporting Channels 5 to 12 in Compliance with IEEE 802.15.4/4z Standards
        10.5 A 28nm Multimode Multiband RF Transceiver with Harmonic-Rejection TX and Spur-Avoidance RX Supporting LTE Cat1bis
Session 11: RF and mm-Wave Wireless Receivers
        11.1 A 256-Element Ka-Band CMOS Phased-Array Receiver Using Switch-Type Quadrature-Hybrid-First Architecture for Small Satellite
        11.2 A Blocker-Tolerant Receiver with VCO-Based Non-Uniform Multi-Level Time-Approximation Filter with -36dB EVM in 28nm CMOS
        11.3 A Compact Full-Duplex Receiver with Wideband Multi-Domain Hilbert-Transform-Equalization Cancellation Based on Multi-Stage
        11.4 A Gm-C RF Quadrature-Current-Generation Technique with 40dB IRR in 0.65V 2mW Multi-Mode CMOS GNSS Receiver
        11.5 A 200MHz-BW Blocker-Tolerant Receiver with Fifth-Order Filtering Achieving 19dBm Adjacent-Channel IIP3
Session 12: Innovations from Outside the (ISSCC’s) Box
        12.1 Circuits that Solve Optimization Problems by Exploiting Physics Inequalities
        12.2 p-Circuits: Neither Digital nor Analog
        12.3 Reversing Scattering to Perform Deep-Tissue Optical Imaging and the Current Need for a Suitable Optoelectronic Solution
        12.4 Skin-Inspired Electronics: An Emerging Sensing and Computing Platform
Session 13: Cool Computation Circuits
        13.1 A 0.22mm2 161nW Noise-Robust Voice-Activity Detection Using Information-Aware Data Compression and Neuromorphic Spatial-Tem
        13.2 An 8.62μW 75dB-DRSoC End-to-End Spoken-LanguageUnderstanding SoC with Channel-Level AGC and Temporal-Sparsity-Aware Streami
        13.3 A Cryo-BiCMOS Controller for
        13.4 Xiling: Cryo-CMOS 18-bit Dual-DAC Manipulator with 4.6μV Precision and 4.1nV/Hz0.5 Noise Co-Integrated with the Single Elec
        13.5 An 18.5μW/qubit Cryo-CMOS Charge-Readout IC Demonstrating QAM Multiplexing for Spin Qubits
        13.6 A Via-Programmable DNN-Processor Fabrication Toward 1/40th Mask Cost
Session 14: Compute-in-Memory
        14.1 A 22nm 104.5TOPS/W μ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks
        14.2 A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices
        14.3 A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two’s-Complement MAC for CNNs and Trans
        14.4 A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and <2-
        14.5 A 28nm 192.3TFLOPS/W Accurate/Approximate Dual-Mode-Transpose Digital 6T-SRAM CIM Macro for Floating-Point Edge Training an
        14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity
        14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dua
Session 15: Neural Interfaces and Edge Intelligence for Medical Devices
        15.1 A 3.9mW 200words/min Neural Signal Processor in Speech Decoding for Brain-Machine Interface
        15.2 A 1024-Channel 0.00029mm2/ch 74nW/ch Online Spatial Spike-Sorting Chip with Event-Driven Spike Detection and Self-Organizin
        15.3 A 65nm Uncertainty-Quantifiable Ventricular Arrhythmia Detection Engine with 1.75μJ per Inference
        15.4 A Neuroprosthetic SoC with Sensory Feedback Featuring Frequency-Splitting-Based Wireless Power Transfer with 200Mb/s 0.67pJ
        15.5 Event-Based Spatially Zooming Neural Interface IC with 10nW/Input Reconfigurable-Inverter Fabric and Input-Adaptive Quantiz
        15.6 A 3.47 NEF 175.2dB FOMS Direct Digitization Front-End Featuring Delta Amplification for Enhanced Dynamic Range and Energy E
        15.7 A 4.6μW 3.3-NEF Biopotential Amplifier with 133VPP Common-Mode Interference Tolerance and 102dB Total Common-Mode Rejection
Session 16: Highlighted Chip Releases: Digital and Machine Learning Processors
        16.1 Tomahawk5: 51.2Tb/s 5nm Monolithic Switch Chip for AI/ML Networking
        16.2 RNGD: A 5nm Tensor-Contraction Processor for Power-Efficient Inference on Large Language Models
        16.3 An On-Device Generative AI Focused Neural Processing Unit in 4nm Flagship Mobile SoC with Fan-Out Wafer-Level Package
        16.4 SambaNova SN40L: A 5nm 2.5D Dataflow Accelerator with Three Memory Tiers for Trillion Parameter AI
Session 17: Hardware Security
        17.1 Sensor-Less Laser Voltage-Probing Attack Detection via Run-Time-Leakage-Shift Monitoring with 4.35% Area Overhead
        17.2 A 28nm 4.05μJ/Encryption 8.72kHMul/s Reconfigurable Multi-Scheme Fully Homomorphic Encryption Processor for Encrypted Clien
        17.3 A 30.4GOPS/mW MK-CKKS Processor for Secure Multi-Party Computation
        17.4 An Efficient Vth-Tilting PUF Design in 3nm GAA and 8nm FinFET Technologies
        17.5 An Eye-Opening Arbiter PUF for Fingerprint Generation Using Auto-Error Detection for PVT-Robust Masking and Bit Stabilizati
        17.6 A 100MHz Self-Calibrating RC Oscillator Capable of Clock-Glitch Detection for Hardware Security in a 3nm FinFET Process
Session 18: Noise-Shaping and SAR-Based ADCs
        18.1 A Fully Dynamic Noise-Shaping SAR ADC Achieving 120dB SNDR and 189dB FoMS in 1kHz BW
        18.2 A 12.2μW 99.6dB-SNDR 184.8dB-FOMS DT Zoom PPD
        18.3 A 93.3dB SNDR, 180.4dB FoMS Calibration-Free Noise-Shaping Pipelined-SAR ADC with Cross-Stage Gain-Mismatch-ErrorShaping Te
        18.4 A 184.8dB-FoMS 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Techn
        18.5 A Rail-to-Rail 3rd-Order Noise-Shaping SAR ADC Achieving 105.4dB SFDR with Integrated Input Buffer Using Continuous-Time Co
        18.6 An Easy-Drive 16MS/s Pipelined-SAR ADC Using Split Coarse-Fine Input-Buffer-Sampling Scheme and Fast Robust Background Inte
        18.7 A 70dB SNDR 80MHz BW Filter-Embedded Pipeline-SAR ADC Achieving 172dB FoMS with Progressive Conversion and Floating-Charge-
        18.8 A Cryo-CMOS 800MS/s 7b CI-SAR with only 4fF Input Capacitance and 64dB SFDR
Session 19: Frequency Synthesizers and Series-Resonance VCOs
        19.1 A PVT-Robust 5.5GHz Fractional-N Cascaded RO-Based Digital PLL with Voltage-Domain Feedforward Noise Cancellation
        19.2 A 96fsrms-Jitter, -70.6dBc-Fractional-Spur Cascaded PLL Employing Two MMDs with Shared DSM for Quantization Noise Cancellat
        19.3 A Fractional-N PLL with 34fsrms Jitter and -255.5dB FoM Based on a Multipath Feedback Technique
        19.4 An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscillator Achieving -128.7dBc/Hz PN at 1MHz
        19.5 A Differential Series-Resonance CMOS VCO with Pole-Convergence Technique Achieving 202.1dBc/Hz FoMTA at 10MHz Offset
        19.6 A 60GHz I/Q-Calibrated SSB-Mixer-Based LO with Sub-ns Settling Time and -56dBc Worst-Case Spur Using ILO Filter in 28nm CMO
        19.7 A 27GHz Fractional-N Sub-Sampling PLL Achieving 57.9fsrms Jitter, -249.7dB FoM, and 1.98μs Locking Time Using a Polarity-Re
        19.8 A 0.65V-VDD 10.4-to-11.8GHz Fractional-N Sampling PLL Achieving 73.8fsrms Jitter, -271.5dB FoMN, and -61dBc In-band Fractio
        19.9 An 11-to-16.4GHz, 3.4GHz/μs-Slope, 5.32GHz-Chirp-Bandwidth, 0.043%-RMS-Frequency-Error FMCW Digital PLL with Posterior-Segm
        19.10 A 4.6GHz 63.3fsrms PLL-XO Co-Design Using a Self-Aligned Pulse-Injection Driver Achieving -255.2dB FoMJ Including the XO P
        19.11 A 13GHz Charge-Pump PLL Achieving 15.8fsrms Integrated Jitter and -98.5dBc Reference Spur
Session 20: Sensors and Actuators for Health & Autonomy
        20.1 A 3.5×3.5mm2 1.47mW/ch 16-Channel MSS-CMOS Heterogeneous Multi-Modal-Gas-Sensor Chip Stack
        20.2 A 67μW/channel, 0.13nW/synapse/b Nose-on-a-Chip for Noninvasive Diagnosis of Diseases with On-Chip Incremental Learning
        20.3 An RFID-Inspired One-Step Packaged Multimode Bio-Analyzer with Vacuum Microfluidics for Point-of-Care Diagnostics
        20.4 MEMS-Free 4096-Pixel CMOS E-Nose Gas-Sensor Array with Molecular-Selective Metal-Organic-Framework Sensing and In-Pixel The
        20.5 Millimeter-Sized 0.1pM LoD Wireless 16-Channel Organic-Electrochemical-Transistor-Based Electrochemical Sensing SoC
        20.6 Fully Integrated Self-Propelling Microrobot in 180nm CMOS with Sub-GHz Parity-Time-Symmetry On-Chip Energy Harvesting and T
        20.7 A 384-Site Chip Platform for Biochemical Applications with Individual Site Precision Temperature Control
        20.8 A 94.8nW Battery-Free Intelligent Silicon Platform Enabling Distributed, Adaptive, and Event-Driven Multimodal Sensing at t
        20.9 An Autonomous and Lightweight Microactuator Driving System Using Flying Solid-State Batteries
        20.10 A 200GHz 200-Pixel 2D Near-Field Imager for Biomedical Applications
        20.11 A Crystal-less BodyID with an Asynchronous Clockless Leakage-Powered Wake-Up Receiver and Over-the-Channel Clock Recovery
        20.12 A 3×3.3mm Configurable
Session 21: Compute and USB Power
        21.1 A 12A 89.3% Peak Efficiency and 26mV Undershoot 12-to-1V Two-Stage Converter with Regulated Resonant Switched-Capacitor Reg
        21.2 A Dual-Input Bidirectional 3-Level Battery Charger with Coarse-Fine VCF Balancing and Wide VCR for Foldable Mobile Applicat
        21.3 A Segmented-Interlacing Multi-Phase Hybrid Converter with Inherently Auto-Balanced ILs and Boosted IL Slew Rate During Load
        21.4 A 97.4%-Peak-Efficiency Always-Half-Inductor-Current Hybrid Bidirectional Converter with Adaptive Target Current Tracking f
        21.5 A Fully Integrated Multi-Phase Voltage Regulator with Enhanced Light-Load-Efficiency Peak of 86%, Featuring an Autonomous M
        21.6 A 2A Fully Analog Distribution LDO with Noise Immunity for an SoC
        21.7 Merging Hybrid and Multi-Phase Topologies: A 6-Phase Triple-Step-Down DC-DC Converter Achieving up to a 60:1 Voltage Conver
        21.8 HOOP: A Scalable Hybrid DC-DC Converter Ring for HighPerformance Computing
        21.9 A 20MHz &1MHz Dual-Loop Non-Uniform-Multi-Inductor Hybrid DC-DC Converter with Specified Inductor Current Allocation and Fa
Session 22: Memory Interface
        22.1 A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 Transceiver Tolerant to Supply Noise, Reference Offset and Crosstalk for Chipl
        22.2 An 850μW 2-to-5GHz Jitter-Filtering and Instant-Toggling Injection-Locked Quadrature-Clock Generator for Low-Power Clock Di
        22.3 A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces
        22.4 A 32-to-50Gb/s/pin Single-Ended PAM-4 Transmitter with a ZQ-Based FFE and PAM-4 LSB DBI-DC Encoding
        22.5 A 0.3pJ/b 32Gb/s/pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer
Session 23: AI-Accelerators
        23.1 T-REX: A 68-to-567μs/Token 0.41-to-3.95μJ/Token Transformer Accelerator with Reduced External Memory Access and Enhanced Ha
        23.2 A 28nm 0.22μJ/Token Memory-Compute-Intensity-Aware CNN-Transformer Accelerator with Hybrid-Attention-Based Layer-Fusion and
        23.3 EdgeDiff: 418.4mJ/Inference Multi-Modal Few-Step Diffusion Model Accelerator with Mixed-Precision and Reordered Group Quant
        23.4 Nebula: A 28nm 109.8TOPS/W 3D PNN Accelerator Featuring Adaptive Partition, Multi-Skipping, and Block-Wise Aggregation
        23.5 MAE: A 3nm 0.168mm2 576MAC Mini AutoEncoder with Line-based Depth-First Scheduling for Generative AI in Vision on Edge Devi
        23.6 MEGA.mini: A Universal Generative AI Processor with a New Big/Little Core Architecture for NPU
        23.7 BROCA: A 52.4-to-559.2mW Mobile Social Agent System-on-Chip with Adaptive Bit-Truncate Unit and Acoustic-Cluster Bit Groupi
        23.8 An 88.36TOPS/W Bit-Level-Weight-Compressed Large-Language-Model Accelerator with Cluster-Aligned INT-FP-GEMM and Bi-Dimensi
        23.9 Slim-Llama: A 4.69mW Large-Language-Model Processor with Binary/Ternary Weights for Billion-Parameter Llama Model
        23.10 HuMoniX: A 57.3fps 12.8TFLOPS/W Text-to-Motion Processor with Inter-Iteration Output Sparsity and Inter-Frame Joint Simila
Session 24: High-Frequency ADCs
        24.1 A 12b 3GS/s Pipelined ADC with Gated-LMS-Based Piecewise-Linear Nonlinearity Calibration
        24.2 A 14b 1GS/s Single-Channel Pipelined ADC with a Parallel-Operation SAR Sub-Quantizer and a DynamicDeadzone Ring Amplifier
        24.3 A PVT-Robust 2× Interleaved 2.2GS/s ADC with Gated-CCRO-Based Quantizer Shared Across Channels and Steps Achieving >4.5GHz
        24.4 A 10b 3GS/s Time-Domain ADC with Mutually Exclusive Metastability Correction and Wide Common-Mode Input
        24.5 A 72GS/s 9b Time-Interleaved Pipeline-SAR ADC Achieving 55.3/49.3dB SFDR at 20GHz/Nyquist Inputs in 16nm FinFET
        24.6 A Powerand Area-Efficient 4nm Self-Calibrated 12b/16GS/s Hierarchical Time-Interleaving ADC
        24.7 An 8b 10GS/s 2-Channel Time-Interleaved Pipelined ADC with Concurrent Residue Transfer and Quantization, and Automatic Buff
        24.8 A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET
Session 25: High-Concepts at High Frequencies
        25.1 A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with
        25.2 A 4GS/s Fully Analog 256×256 MP-Based Cross-Correlator with 1000TOPS/W Compute Efficiency and 1.3TOPS/mm2 Compute Density i
        25.3 AI-Enabled Design Space Discovery and End-to-end Synthesis for RFICs with Reinforcement Learning and Inverse Methods Demons
        25.4 A Micromachined Heterogeneously Integrated Active-Probe Enabling Non-Disruptive In-Situ Measurements from DC to 50GHz
        25.5 A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS
Session 26: Wireless Transmitters and Front-Ends
        26.1 A 24GHz Direct Digital Transmitter Using MultiphaseSubharmonic Switching PA Achieving 3.2Gb/s Data Rateand -30.8dB EVM in 65nm CMOS
        26.2 A Wideband Replicas-Rejection Digital Transmitter Using Joint-Digital-Analog Interpolation and Filtering in 28nm CMOS
        26.3 A Crystal-less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Con
        26.4 A 24-to-29GHz Compact Transmit/Receive Front-End Module Featuring an Asymmetric Doherty Power Amplifier and 0.22mm2 Area
        26.5 A 17.7-to-29.5GHz Transceiver Front-End with 3.3dB NF and 20.2dBm OP1dB in 65nm CMOS
Session 27: Sensor Interfaces
        27.1 A 3-Axis MEMS Gyroscope with 2.8ms Wake-Up Time Enabled by a 1.5μW Always-On Drive Loop
        27.2 A Voltage-Biased CMOS Hall Sensor with 1.0μT (3σ) Offset and a 60nT/√Hz Noise-Floor
        27.3 A Sub-1V 14b 5.8nW/Hz BW/Power-Scalable CT Sensor Interface with a Frequency-Controlled Current Source Achieving a 225× Sca
        27.4 A BJT-Based Temperature Sensor with an 80fJ∙K2 Resolution FoM
        27.5 A 4,100μm2 Wire-Metal-Based Temperature Sensor with a Fractional-Discharge FLL and a Time-Domain Amplifier with ±0.2°C Inac
Session 28: Capacitive Sensor Readout
        28.1 An 18.5nF-Input-Range PM-SAR-Hybrid Capacitance-to-Digital Converter Achieving 6.1μs Conversion Time at 18.1pF Input Capaci
        28.2 A 189.3dB-FoMS 14.5fJ/Conversion-Step Continuous-Time Noise-Shaping SAR Capacitance-to-Digital Converter
        28.3 A 185.2dB-FoMs 8.7aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Su
        28.4 A 143dB-Dynamic-Range 119dB-CMRR Capacitance-to-Digital Converter for High-Resolution Floating-Target Displacement Sensing
Session 29: SRAM
        29.1 A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute
        29.2 A 0.021μm2 High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery
        29.3 A 3nm FinFET 2.2Gsearch/s 0.305fJ/b TCAM with Dynamically Gated Search Lines for Data-Center ASICs
        29.4 A 38Mb/mm2 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology
        29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme
Session 30: Nonvolatile Memory and DRAM
        30.1 A 28Gb/mm2 4XX-Layer 1Tb 3b/cell WF-Bonding 3D-NAND Flash with 5.6Gb/s/pin IOs
        30.2 A 1Tb 3b/cell 3D-Flash Memory with a 29%-Improved-EnergyEfficiency Read Operation and 4.8Gb/s Power-Isolated Low-Tapped-Ter
        30.3 A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhan
        30.4 A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5th-Ge
        30.5 A 321-Layer 2Tb 4b/cell 3D-NAND-Flash Memory with a 75MB/s Program Throughput
        30.6 A 64Gb DDR4 STT-MRAM Using a Time-Controlled Discharge-Reading Scheme for a 0.001681μm2 1T-1MTJ Cross-Point Cell
Session 31: Energy Harvesting and IoT Power
        31.1 An Inductor-less Capacitor-less Synchronous PiezoelectricElectromagnetic Hybrid Energy Harvesting Platform with Coil-Sharin
        31.2 A Biased-SECE Interface for Piezoelectric Energy Harvesting with Geometric-Mean-Computational MPPT Achieving 99.9% MPPT Eff
        31.3 A Rectifier-less Piezoelectric Energy-Harvesting Interface with a Sense & Track MPPT Achieving Single-Cycle Convergence and
        31.4 A 91.25% Peak Power-Conversion-Efficiency Capacitive PowerManagement IC Supporting up to 5.68mJ Burst Energy Delivery Using
Session 32: Isolated Power and Gate Drivers
        32.1 A 180MHz 45.3%-Peak-Efficiency Isolated Converter Using Q-Downsize Class-D Power Amplifier with Inherent Shoot-Through Curr
        32.2 A Single-Link Multi-Domain-Output (SLiMDO) Isolated DC-DC Converter with Passive Magnetic Flux Sharing for Local Energy Dis
        32.3 An Accurate Secondary-Side Controller with GaN-Based CGS Isolated Driver Achieving Sub-1% Error On-Chip Sensing
        32.4 A Dual-LC-Resonant Isolated DC-DC Converter Achieving 65.4% Peak Efficiency and Inherent Backscattering
        32.5 A 2W 53.2%-Peak-Efficiency Multi-Core Isolated DC-DC Converter with Embedded Magnetic-Core Transformer Achieving CISPR-32 C
        32.6 A Dynamic-RON-Diminished Bidirectional GaN Load Switch with Inrush Current Protection and Spike Attenuation
Session 33: Components for Beyond 100GHz
        33.1 A 232-to-260GHz CMOS Amplifier-Multiplier Chain with a Low-Cost, Matching-Sheet-Assisted Radiation Package and 11.1dBm Tota
        33.2 A 216-to-226GHz Watt-Level GaN Solid-State Power Amplifier with Multiband Large-Signal Impedance Correction and Circuit-Pac
        33.3 A 125-to-170GHz Power-Efficient Phase Shifter in SiGe BiCMOS with Outphasing Gain and Phase Corrections
        33.4 A Wideband Bidirectional Calibration-Free Frequency/Switching-Staggering 360° D-Band Phase Shifter with Frequency-Invariant
        33.5 A 224GHz 19.9% TR Varactor-less VCO Utilizing a Multi-Section Switch-Loaded Coupled-Line Resonator
Session 34: Digital PLLs and Waveform-Shaping VCOs
        34.1 A 65fsrms-Jitter and -272dB-FoMjitter,N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration
        34.2 A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy
        34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adapt
        34.4 A 9.05-to-37.0GHz LO Generator with Magnetic Mode Switching and Tuning-Free Octave-Bandwidth Common-Mode Resonator Achievin
        34.5 An 18.5-to-23.6GHz Quad-Core Class-F23 Oscillator Without 2nd/3rd Harmonic Tuning Achieving 193dBc/Hz Peak FoM and 140-to-2
        34.6 A 47.3-to-58.4GHz Differential Quasi-Class-E Colpitts Oscillator Achieving 198.8dBc/Hz FoMT
Session 35: Implantable and Wearable Biomedical Devices
        35.1 A Single-Inductor-Based High-Voltage Transmit Beamformer for Wearable Ultrasound Devices Achieving 88% fCV2 Power Reduction
        35.2 A Spatial-Domain Compressive-Sensing Photoacoustic Imager with Matrix-Multiplying SAR ADC
        35.3 A 30MHz Wideband 92.7dB SNR 99.6% Accuracy Bioimpedance Spectroscopy IC Using Time-to-Digital Demodulation with Co-Prime De
        35.4 A Miniature Biomedical Implant Secured by Two-Factor Authentication with Emergency Access
        35.5 A Wireless Adiabatic Stimulator System with Current-Mode Power Reception and Stimulus Current Regulation Achieving Precise
        35.6 An Enhanced-Frequency-Splitting-Based Wireless Power and Data Transfer System Achieving 60.2% End-to-End Efficiency and 1Mb
        35.7 A Programming-Free Three-Dimensional Resonant Current-Mode Wireless Receiver with Real-Time Link-Adaptivity and a 0.904cm3
        35.8 DustNet: A Network of Time-Division Multiplexed Ultrasonic Implants with 16-Level ASK Backscatter Modulation
Session 36: Ultra-High-Density D2D and High-Performance Optical Transceivers
        36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating
        36.2 A 64Gb/s/wire 10.5Tb/s/mm/layer Single-Ended Simultaneous Bi-Directional Transceiver with Echo and Crosstalk Cancellation f
        36.3 A 0.29pJ/b 5.27Tb/s/mm UCIe Advanced Package Link in 3nm FinFET with 2.5D CoWoS Packaging
        36.4 A 0.9pJ/b 108Gb/s PAM-4 VCSEL-Based Direct-Drive Optical Engine
        36.5 A Low-Latency 200Gb/s PAM-4 Heterogeneous Transceiver in 0.13μm SiGe BiCMOS and 28nm CMOS for Retimed Pluggable Optics
        36.6 A 112Gb/s 0.61pJ/b PAM-4 Linear TIA Supporting Extended PD-TIA Reach in 28nm CMOS
        36.7 A 1.54pJ/b 64Gb/s 16-QAM Intradyne Coherent Optical Receiver in 28nm CMOS
        36.8 A 100Gbaud 4Vppd Distributed Linear Driver with Cross-Folded Transmission Lines and Cross-Coupled Gm Cells for Built-in 5-T
        36.9 A 212Gb/s PAM-4 Retimer with Integrated High-Swing Optical Driver and Chip-to-Module Long Reach Capability of 40dB in 5nm F
Session 37: Design-Technology Optimization and Digital Accelerators
        37.1 IBM Telum II Processor Design-Technology Co-Optimizations for Power, Performance, Area, and Reliability
        37.2 A 2-Dimensional mm-Scale Network-on-Textiles (kNOTs) for Wearable Computing with Direct Die-to-Yarn Integration of 0.6×2.15
        37.3 Monolithic In-Memory Computing Microprocessor for End-to-End DNN Inferencing in MRAM-Embedded 28nm CMOS Technology with 1.1
        37.4 SHINSAI: A 586mm2 Reusable Active TSV Interposer with Programmable Interconnect Fabric and 512Mb 3D Underdeck Memory
        37.5 SKADI: A 28nm Complete K-SAT Solver Featuring Dual-Path SRAM-Based Macro and Incremental Update with 100% Solvability
        37.6 A 22nm 60.81TFLOPS/W Diffusion Accelerator with Bandwidth-Aware Memory Partition and BL-Segmented Compute-in-Memory for Eff
        37.7 A 28nm 18.1μJ/Acquisition End-to-End GPS Acquisition Accelerator with Energy-Accuracy-Driven Mixed-Radix IFFT and ROM-Assis
        37.8 A 13.5μW 35-Keyword End-to-End Keyword Spotting System Featuring Personalized On-Chip Training in 28nm CMOS

azen812

Really thanks a lot, do u have visual file?

zhouyang2018

学习中 要是有PPT就更好了

hungda00

thanks for sharing

argento

Many thanks

Vodka_JON7

信元啊

remix1130

Many thank you for your generous sharing!

gps66

很不错哦哦

jianchongzhou

Thank you very much.

gps66

很棒的内容谢谢