dc如何实现verilog、vhdl混合综合？

吕归尘

我在读入vhdl和verilog如下写法：

analyze -f sv -lib WORK ${verilog_filelist}
analyze -f vhdl -lib WORK ${vhdl_filelist}
elaborate -lib WORK -update $top
也尝试了下面这种：

analyze -f sv -lib WORK ${verilog_filelist}
elaborate -lib WORK -update $top
analyze -f vhdl -lib WORK ${vhdl_filelist}
elaborate -architecture vhdl -lib WORK -update $top


这两种写法好像都没法把vhdl和verilog一起综合，会提示：
cannot find the design "VHDL的文件" in the library WORK.(LBR-1)

zhiwenhao

不指定语法类型，用-autoread

puxiancheng

analyze -format vhdl -vcs {-f vhdl.f}
analyze -format verilog -vcs {-f verilog.f}
elaborate $top