Cadence Course Mixed Signal Verification with UVM Training

mesmerism

thanks for sharing

cyberwillis

thanks

DT27

   

cxmm17 发表于 2025-2-11 23:41
Dear @DT27

https://www.cadence.com/en_US/home/training/all-courses/86140.html

Cadence Course Essential SystemVerilog for UVM v1.2.5
https://bbs.eetop.cn/thread-983805-1-1.html

Cadence Course SystemVerilog Accelerated Verification using UVM
https://bbs.eetop.cn/thread-983806-1-1.html

Cadence Course SystemVerilog Assertions​ Version 5.1
https://bbs.eetop.cn/thread-983808-1-1.html

cxmm17

   

DT27 发表于 2025-2-13 15:11
Cadence Course Essential SystemVerilog for UVM v1.2.5
https://bbs.eetop.cn/thread-983805-1-1.html
...

Dear @DT27

Thank you very much for your contribution to the community. Wishing you a healthy, happy and joyful new year

leejohannes

感谢无私分享

bruce2246

Thanks~~~

mi_smart

感谢分享

DT27

   

cxmm17 发表于 2025-2-14 10:07
Dear @DT27

Thank you very much for your contribution to the community. Wishing you a healthy, ha ...

u're welcome brother~ Wish u have a great year too~

whoami123

thank you for education

fox1012

多谢分享