【Verilog语言经典图书下载】Design Through Verilog HDL

vertyang

Design Through Verilog HDL
by T. R. Padmanabhan, B. Bala Tripura Sundari,  

--------------------------------------------------------------------------------
engmsaleh, 357 days ago         


--------------------------------------------------------------------------------
By T. R. Padmanabhan, B. Bala Tripura Sundari,

Publisher:   Wiley-IEEE Press
Number Of Pages:   472
Publication Date:   2003-11-05
Sales Rank:   635027
ISBN / ASIN:   0471441481
EAN:   9780471441489
Binding:   Hardcover
Manufacturer:   Wiley-IEEE Press
Studio:   Wiley-IEEE Press
Average Rating:   
Total Reviews:   

--------------------------------------------------------------------------------
Book Description: )
A comprehensive resource on Verilog HDL for beginners and experts
Large and complicated digital circuits can be incorporated into hardware by using Verilog, a hardware description language (HDL). A designer aspiring to master this versatile language must first become familiar with its constructs, practice their use in real applications, and apply them in combinations in order to be successful. Design Through Verilog HDL affords novices the opportunity to perform all of these tasks, while also offering seasoned professionals a comprehensive resource on this dynamic tool.
Describing a design using Verilog is only half the story: writing test-benches, testing a design for all its desired functions, and how identifying and removing the faults remain significant challenges. Design Through Verilog HDL addresses each of these issues concisely and effectively. The authors discuss constructs through illustrative examples that are tested with popular simulation packages, ensuring the subject matter remains practically relevant.
Other important topics covered include:
Primitives
Gate and Net delays
Buffers
CMOS switches
State machine design
Further, the authors focus on illuminating the differences between gate level, data flow, and behavioral styles of Verilog, a critical distinction for designers. The book's final chapters deal with advanced topics such as timescales, parameters and related constructs, queues, and switch level design.
Each chapter concludes with exercises that both ensure readers have mastered the present material and stimulate readers to explore avenues of their own choosing. Written and assembled in a paced, logical manner, Design Through Verilog HDL provides professionals, graduate students, and advanced undergraduates with a one-of-a-kind resource.

[ 本帖最后由 vertyang 于 2008-2-29 17:57 编辑 ]

denap

Thanks for sharing!!

sycall

下来看看，谢谢

mingho

thanks

0xffff

好东西
谢谢楼主

minidust

谢谢楼主！

yel27

louazhu haoren

0xffff

好书啊:lol:lol:lol

weird

什么书，下来看看！！

ewb1

什么书，下来看看！！