初学版图设计，做LVS时遇到了问题，求各位大神解答

ljh1213817 · 发表于昨天 19:52

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               CELL COMPARISON RESULTS ( TOP LEVEL )

               # #       #####################
               # #       #                #
                  #          #    INCORRECT    #
               # #       #                #
               # #       #####################

  Error: Connectivity errors.

LAYOUT CELL NAME:       inverter
SOURCE CELL NAME:       inverter

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS
--------------------------

            Layout Source       Component Type
            ------ ------       --------------
Ports:             4       4

Nets:             6       6

Instances:       15       3 * n18_ckt (4 pins)
                  30       3 * p18_ckt (4 pins)
                  1       0 * D (2 pins)
            ------ ------
Total Inst:       46       6

NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------

            Layout Source       Component Type
            ------ ------       --------------
Ports:             4       4

Nets:             4       4

Instances:       1       1       _invx3v (4 pins)
            ------ ------
Total Inst:       1       1

   * = Number of objects in layout different from number in source.

**************************************************************************************************************
                           INFORMATION AND WARNINGS
**************************************************************************************************************

               Matched Matched Unmatched Unmatched Component
               Layout    Source    Layout    Source Type
               ------- ------- --------- --------- ---------
Ports:             4       4          0          0

Nets:             4       4          0          0

Instances:          1       1          0          0 _invx3v
               ------- ------- --------- ---------
Total Inst:       1       1          0          0

o Statistics:

1 passthrough layout net was found.

1 layout instance was filtered and its pins removed from adjoining nets.

45 layout mos transistors were reduced to 6.
   39 mos transistors were deleted by parallel reduction.

o Passthrough Layout Nets And Their Ports:

   (Layout nets which are connected only to ports).

VDD (port: VDD),

o Initial Correspondence Points:

Ports:       VDD VSS IN OUT

fengrlove · 发表于昨天 20:34

上版图看看

ljh1213817 · 发表于昨天 20:58

登录/注册后可看大图

ljh1213817 · 发表于昨天 21:16

版图

fengrlove · 发表于昨天 22:43

本帖最后由 fengrlove 于 2024-12-25 22:44 编辑

ljh1213817 发表于 2024-12-25 21:16
版图

第二张图，pmos为嘛接到VSS，而且没有给B端电位

linkx · 发表于 3 小时前

顶顶

[求助] 初学版图设计，做LVS时遇到了问题，求各位大神解答

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