set reg [filter_collection [all_registers ] "is_integrated_clock_gating_cell != true"]
set inp [all_inputs]
set out [all_outputs]
set mem [filter_collection [all_registers] "is_memory_cell == true"]
set ckgating [filter_collection [all_registers] "is_integrated_clock_gating_cell == true"]
set ignore_path_groups [list inp2reg reg2out feedthr]