请教一个xilinx ip的应用

gzluo

在做一个XILINX RFSOC 设计 ，利用DAC 播放波形 4G/5G  LTE/NR FDD/TDD信号。

利用xilinx 参考设计里 一个timebase tick IP 生成10ms 触发信号 给外部仪表 做trigger 测试TDD信号。
这个IP 输入只有时钟 491.52M 要产生一个10ms trigger. code 里 利用CPRI_frame 信息。
现在设计里 没有CPRI 接口，实测下来 还是能产生一个接近10ms trigger信号，但不是绝对10ms。这样导致做触发仪表时 不能完美同步。

示波器 测量这个信号 99.99Hz . 10ms应该对应100Hz.

请假下：怎么理解code 里 CPRI_frame 信息？

IP readme

The block provides a fixed system tick onto TUSER. The default RTL
provides 4 ticks running at 10ms on m_axis_tuser[3:0], but can be
altered to provide more complex set of timing references.  Data Output
onto TDATA is always zero.



代码：

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--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.dfe_util_pkg.all;


entity dfe_tick is
generic
  (
    C_ANTENNAS               : integer := 1;
    C_DATA_RATE              : integer := 8;
    C_DATA_PHASES            : integer := 1;
    C_TEST_MODE              : integer := 0
  );
port(

  aclk                 : in  std_logic;
  aresetn              : in  std_logic;
  
  m_axis_dout_tdata                    : out std_logic_vector(C_ANTENNAS*C_DATA_PHASES*32-1 downto 0)    := (others=>'0');
  m_axis_dout_tlast                    : out std_logic := '0';
  m_axis_dout_tuser                    : out std_logic_vector(C_ANTENNAS*8-1 downto 0)                   := (others=>'0');
  m_axis_dout_tvalid                   : out std_logic := '0';
  m_axis_dout_tready                   :  in std_logic := '1'
   
);
end dfe_tick;

architecture rtl of dfe_tick is

  
  constant C_SAMPLES_PER_TC                : integer := 8*C_DATA_RATE/C_DATA_PHASES;

  constant C_CPRI_TC_PER_HF                : integer := iff(C_TEST_MODE>0, 256/16, 256);
  constant C_CPRI_HF_PER_FRM               : integer := iff(C_TEST_MODE>0, 150/5,  150);
  constant C_CPRI_N_BFN                    : integer := iff(C_TEST_MODE>0, 4096/1024, 4096);



  -- Ticks
  --
  --
  signal tick_restart : std_logic := '0';


   
  -- Frame Reset
  --
  -- Aligned Reset : releases counters
  signal frame_reset    : std_logic := '0';
  
  -- TC (Chip) Tick Generations
  --
  --
  signal tc_tick           : std_logic := '0';
  signal tc_tick_pre       : std_logic := '0';
  signal tc_sample_count   : std_logic_vector(7 downto 0) := (others => '0');
  signal tc_load_count     : std_logic_vector(7 downto 0) := (others => '0');

  -- CPRI Counters
  --
  --
  signal cpri_tc_count     : std_logic_vector(7 downto 0) := (others => '0');
  signal cpri_tc_max       : std_logic := '0';

  signal cpri_hf_last      : std_logic := '0';

  signal cpri_hf_count     : std_logic_vector(7 downto 0) := (others => '0');
  signal cpri_hf_max       : std_logic := '0';

  signal cpri_fr_last      : std_logic := '0';

  signal cpri_fr_count     : std_logic_vector(11 downto 0) := (others => '0');
  signal cpri_fr_max       : std_logic := '0';

  -- Node-B Frame Number (BFN) load control
  --
  --
  signal bfn_load_tvalid : std_logic := '0';
  signal bfn_load_tdata  : std_logic_vector(11 downto 0) := (others=>'0');

begin



  


  -- Frame reset
  --
  -- reset counters when not in_sync or immediately after sync_in_restart
  frame_reset  <= '1' when aresetn='0' else '0';
  tick_restart <= frame_reset;

  -- Tc (Chip) Tick
  --
  -- This provides basic tick for counting chips Tc in the design
  -- Corresponds to Basic Frame in CPRI.
  --
  -- Clock Rates :   30.72 MHz =   8 x Tc
  --                245.76 MHz =  64 x Tc
  --                491.52 MHz = 128 x Tc

  tc_load_count <= std_logic_vector(to_unsigned(C_SAMPLES_PER_TC-1,tc_load_count'length));
   
  i_tc_tick: entity work.dfe_time_tick
    generic map (
        C_COUNT_WIDTH => tc_sample_count'length)
    port map (
        clk        => aclk,
        enable     => '1',

        load_count => tc_load_count,
        
        tick_reset => frame_reset,

        tick       => tc_tick,
        tick_pre   => tc_tick_pre,
        tick_count => tc_sample_count);

  
  -- CPRI TC Counter
  --
  -- Counts TCs in a CPRI Hyperframe
  
  i_cpri_tc_count: entity work.dfe_time_counter
    generic map (
        C_COUNT_WIDTH => cpri_tc_count'length,
        C_COUNT0      => C_CPRI_TC_PER_HF,
        C_SUBCOUNTS   => 0)
    port map (
        clk           => aclk,
        enable        => '1',
        
        tick_base     => tc_tick,
        tick_base_pre => tc_tick_pre,
        tick_frame    => frame_reset,

        max_in        => "1",

        count         => cpri_tc_count,
        max_out       => cpri_tc_max,

        last          => cpri_hf_last);

  -- CPRI Hyperframe Counter
  --
  -- Counts Hyperframes in a CPRI Frame
  
  i_cpri_hf_count: entity work.dfe_time_counter
    generic map (
        C_COUNT_WIDTH => cpri_hf_count'length,
        C_COUNT0      => C_CPRI_HF_PER_FRM,
        C_SUBCOUNTS   => 1,
        C_MAX_IN_WIDTH => 1)
    port map (
        clk           => aclk,
        enable        => '1',
        
        tick_base     => tc_tick,
        tick_base_pre => tc_tick_pre,
        tick_frame    => frame_reset,

        max_in(0)     => cpri_tc_max,

        count         => cpri_hf_count,
        max_out       => cpri_hf_max,

        last          => cpri_fr_last);


  -- Node-B frame number load control signals
  --
  -- in slave  mode copy BFN on input to this count
  -- in master mode, do not load this value
  bfn_load_tvalid <= '0';
  bfn_load_tdata  <= (others=>'0');
  
  -- CPRI Frame Counter
  --
  -- Counts CPRI Frames to generate NodeB Frame Number
  
  i_cpri_fr_count: entity work.dfe_time_counter
    generic map (
        C_COUNT_WIDTH => cpri_fr_count'length,
        C_COUNT0      => C_CPRI_N_BFN,
        C_SUBCOUNTS   => 2,
        C_MAX_IN_WIDTH => 2)
    port map (
        clk           => aclk,
        enable        => '1',
        
        tick_base     => tc_tick,
        tick_base_pre => tc_tick_pre,
        tick_frame    => tick_restart,

        load_tvalid   => bfn_load_tvalid,
        load_tdata    => bfn_load_tdata,
        
        max_in(0)     => cpri_tc_max,
        max_in(1)     => cpri_hf_max,

        count         => cpri_fr_count,
        max_out       => cpri_fr_max,

        last          => open);

  



  -- TLAST/TUSER Output Options
  --
  --


  -- TVALID Output
  --
  --
  m_axis_dout_tvalid             <= '1';

  -- TDATA Output
  --
  --
  m_axis_dout_tdata              <= (others=>'0');
  
  -- TLAST Output
  --
  --
  m_axis_dout_tlast              <= cpri_hf_last;
   
  -- TUSER Output
  --
  --

  p_tuser: process (cpri_fr_last)
  begin
    for i in 0 to C_ANTENNAS-1 loop

      -- TUSER is one-byte per antenna
      -- allocation of bits in each byte are:
      -- bits  7:5: not used
      -- bit     4: TDD Enable
      -- bit     3: Restart Marker / Capture Sync
      -- bit     2: Alternate Frame Marker (e.g. use for GSM framing if  required)
      -- bit     1: Frame Marker
      -- bit     0: Slot Marker
      m_axis_dout_tuser(i*8+7 downto i*8)  <= "0000" & cpri_fr_last & cpri_fr_last & cpri_fr_last & cpri_fr_last;

    end loop;
  end process p_tuser;

end rtl;

flyger

时钟同源了么 没有的话弄个参考时钟同源下试试