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本帖最后由 JekinBrown 于 2024-10-18 23:23 编辑
由于后仿时需要在仿真中添加后仿节点,而为了便于添加,需要将寄生网表变得“可读”,也就是层级(hierarchy)和名称(names)要对应上原理图(schematic)的层级和名称。这就需要在提参时保留层级或名称。
calibre提参时在outputs中有如图所示的选项:
在UG(Standard Verification Rule Format (SVRF) Manual, v2023.4)中可以找到如下的解释(或者鼠标指针悬停也有显示,不过UG更加详细):
LAYOUTNAMES — Specifies the names are derived from the layout. SOURCENAMES [filename] — Specifies the names are derived from the schematic or netlist, but the hierarchy is based on the layout. When specifying the SOURCENAMES option, make sure that a valid Source Primary statement identifying a valid primary cell is in the rule file. Also be sure that the naming conventions used in the source are compatible with your output netlist format. Parameters that exist only in the source netlist are copied to the output netlist, even if these parameters are not extracted. SOURCEBASED — Specifies the formatter to use the circuit pin order and cell hierarchy in the source netlist instead of the layout netlist when generating the extracted netlist. If you are creating the source netlist with the Calibre nmLVS software, you must use Calibre nmLVS-H. The design must pass LVS. SCHEMATICONLY [filename] — Specifies a parasitic netlist based on the LVS source hierarchy, with intentional device parameters extracted and backannotated from the layout. Parasitics are netlisted only for nets that are cross-referenced to the source netlist. If filename is not used, only standard parameters for MOSFETs are backannotated. Other devices use source parameters.
虽然读这个UG的解释似乎能get到它们之间的区别,但实际小弟用后三种方式分别提取了寄生,实在是没有get到这三者的显著区别。 例如,我的设计有三个层次,对应的电路原理图网表(src netlist)有三个subckt A B C,A为顶层,B为次顶层,C为最低层;C就是由基础的mos管搭建的电路,内含N个节点。 简单一点说吧,顶层为A,实例名A;A包含两个B,B_1,B_2;B包含3个C,C_1,C_2,C_3. 但无论哪一种提取方式,寄生网表都是只有一个subckt顶层A,然后所有的节点展平。
.subckt A [端口] …… B_1/C_1/<mos管1> B_1/C_1/<mos管2> B_1/C_2... B_2/.... …… [其他互联的次顶层节点] …… [MOS管的例化] .ends
小弟很疑惑,这也并不像UG中说的“use the circuit pin order and cell hierarchy in the source netlist”,和电路原理图网表一致。这三者除了一些顺序有区别,其他小弟也没有看出有什么显著区别。 请各位赐教!
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