|
Starting with the Q-2020.03-1 release version of the Synplify tool, prototyping
features are not supported in the Synplify tool for AMD/Xilinx VU19P and
Versal devices, or for Intel/Altera Agilex 7 and Stratix-10 10M devices. These
prototyping features include, Gated Clock Conversion (GCC), Netlist Editing,
DesignWare component mapping, Bind and Force, Unified Power Format
(UPF). For FPGA-based prototyping, consider using the Synopsys HAPS
product family. For more information, contact Synopsys support. |
|