It seems that the SystemVerilog compile option was not used. If that's the case, sum, pi, gi, and ci should be declared as reg, and pi and gi cannot be declared as reg and have their values assigned using assign.
Error (10170): Verilog HDL syntax error at test1.v(17) near text: "="; expecting ".", or an identifier. Check for and fix any syntax errors that appear immediately before or at the specified keyword.