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本帖最后由 njupt_nzt 于 2024-5-29 10:19 编辑
请问一下,在vcs中进行数字版图后仿真时,为什么有些逻辑功能是正常的,而有些是未知态,这是什么原因造成的?
run.log里边有些违例,有点看不明白
"scc018v3ebcd_uhd_rvt.v", 10827: Timing violation in output_interface_tb.out1.UVW1.R1_REG
$hold( posedge CK &&& (ENABLE_RDN == 1'b1):70010, posedge D &&& (ENABLE_RDN == 1'b1):70010, limit: 10 );
"scc018v3ebcd_uhd_rvt.v", 10827: Timing violation in output_interface_tb.out1.ABZ1.R1_REG
$hold( posedge CK &&& (ENABLE_RDN == 1'b1):70010, posedge D &&& (ENABLE_RDN == 1'b1):70010, limit: 10 );
"scc018v3ebcd_uhd_rvt.v", 10824: Timing violation in output_interface_tb.out1.ABZ1.R1_REG
$hold( posedge CK &&& (ENABLE_RDN == 1'b1):138870010, negedge D &&& (ENABLE_RDN == 1'b1):138870010, limit: 10 );
"scc018v3ebcd_uhd_rvt.v", 10827: Timing violation in output_interface_tb.out1.ABZ1.R1_REG
$hold( posedge CK &&& (ENABLE_RDN == 1'b1):277670010, posedge D &&& (ENABLE_RDN == 1'b1):277670010, limit: 10 );
"scc018v3ebcd_uhd_rvt.v", 10824: Timing violation in output_interface_tb.out1.ABZ1.R1_REG
$hold( posedge CK &&& (ENABLE_RDN == 1'b1):416470010, negedge D &&& (ENABLE_RDN == 1'b1):416470010, limit: 10 );
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