【课程通知】高性能、高速ADC设计课程@陈知行教授

yxysunshine

2024年07月16日—17日 （两天，星期二-星期三）  

Lecture 1:  Time Interleaver and Massive Time Interleaver (3 hours):
-        Application and Technology Motivations
-        Time-Interleaved Non-idealities
-        Front-End Interleaver Topologies
-        Topology Variety Considerations
-        Modeling of Interleaver
-        Uncertainties and Case Studies
Lecture 2: Wideband Input Buffer and Fast-transient Reference Buffer (2 hours)
-        Input Network
-        Nonlinearities
-        Input Buffer Topologies
-        Linearization Techniques
-        Reference Ripple
-        Reference Buffer Topologies
-        Ripple Suppression Techniques
-        Case Studies
Lecture #3 – Wideband Samplers (1 hour)
-        Sampling Theory
-        Sampler Non-idealities
-        Bootstrapped Circuits
Lecture #4 – Clocking and Extreme Amplifier Overview (2 hours)
-        Effect of Jitter on Sampling
-        Low Jitter Clock Receivers
-        Power Efficient and Low Jitter CMOS Clock Buffer
-        Open-Loop Residue Amplifiers
-        Close-Loop Residue Amplifiers
Lecture #5 – State-of-the-Art Low-Resolution High-Speed SAR ADCs (2 hours)
-        Single-bit/cycle
-        Multi-bit/cycle
-        DAC Implementation
-        SAR Loop
-        SAR Switching Logic
-        Redundancy
-        Case Studies
Lecture #6 – Extended Resolution and High-Speed: Pipeline-SAR ADCs (2 hours)
-        Fundamentals
-        Comparison with SAR ADCs
-        Digital Error Correction
-        Residue Amplification Errors
-        Case Studies

yxysunshine

yxysunshine

yxysunshine

yxysunshine

yxysunshine

yxysunshine

yxysunshine

yxysunshine

yxysunshine

报名中哦