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发表于 2024-6-5 13:50:34
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UVM白皮书
我是看了白皮书7.3.5的例子,发现里面bus_driver的run_phase;my_driver的main_phase;my_model的main_phase都有while(1),但是没有看到drop_objection,所以猜是不是有默认仿真时间结束了这些phase
我最近看到网上有提到在sequence里控制objection,这会控制driver里的phase吗?
以下是my_model的代码
class my_model extends uvm_component;
uvm_blocking_get_port #(my_transaction) port;
uvm_analysis_port #(my_transaction) ap;
reg_model p_rm;
extern function new(string name, uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern virtual task main_phase(uvm_phase phase);
extern virtual function void invert_tr(my_transaction tr);
`uvm_component_utils(my_model)
endclass
function my_model::new(string name, uvm_component parent);
super.new(name, parent);
endfunction
function void my_model::build_phase(uvm_phase phase);
super.build_phase(phase);
port = new("port", this);
ap = new("ap", this);
endfunction
function void my_model::invert_tr(my_transaction tr);
tr.dmac = tr.dmac ^ 48'hFFFF_FFFF_FFFF;
tr.smac = tr.smac ^ 48'hFFFF_FFFF_FFFF;
tr.ether_type = tr.ether_type ^ 16'hFFFF;
tr.crc = tr.crc ^ 32'hFFFF_FFFF;
for(int i = 0; i < tr.pload.size; i++)
tr.pload = tr.pload ^ 8'hFF;
endfunction
task my_model::main_phase(uvm_phase phase);
my_transaction tr;
my_transaction new_tr;
uvm_status_e status;
uvm_reg_data_t value;
super.main_phase(phase);
p_rm.invert.read(status, value, UVM_FRONTDOOR);
while(1) begin
port.get(tr);
new_tr = new("new_tr");
new_tr.copy(tr);
//`uvm_info("my_model", "get one transaction, copy and print it:", UVM_LOW)
//new_tr.print();
if(value)
invert_tr(new_tr);
ap.write(new_tr);
end
endtask
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