大部分都是金属密度，芯片密度，最小局部密度等等问题。。。。。。。 1. OD.DN.1 { @ {OD OR DOD} density across full chip >= 25% DENSITY ALL_OD CHIP < OD_DN_1 INSIDE OF LAYER CHIPx [ AREA(ALL_OD)/AREA(CHIP) ] PRINT OD.DN.1.density } 2. OD.DN.2 { @ Min. OD density over window 150 step 75 >= 20% ERR_WIN = DENSITY ODx CHIP_NOT_ODEXC < OD_DN_2 WINDOW OD_DN_2_W STEP OD_DN_2_S INSIDE OF LAYER CHIPx BACKUP [ AREA(ODx)/AREA(CHIP_NOT_ODEXC) ] F = WITH WIDTH (ERR_WIN NOT OD_EXC) >= OD_DN_2_E DENSITY F ODx CHIP_NOT_ODEXC < OD_DN_2 WINDOW OD_DN_2_W STEP OD_DN_2_S INSIDE OF LAYER CHIPx BACKUP PRINT OD.DN.2.density [ !AREA(F)+AREA(ODx)/AREA(CHIP_NOT_ODEXC) ] } 3. PO.DN.1 { @ Min. POLY density across full chip 14% DENSITY ALL_POLY CHIP < PO_DN_1 INSIDE OF LAYER CHIPx [ AREA(ALL_POLY)/AREA(CHIP) ] PRINT PO.DN.1.density } 4. DPO.R.1 { @ DPO is must. DPO must be an individual CAD layer (datatype 1 as default, like 17;1) CHIPx NOT INTERACT DPO } 5. M1.DN.1 { @ Minimum local density [window 125 um x 125 um, stepping 62.5 um] >= 0.1 M1_CHECK = M1x NOT M1_EXC_LOW CHIP_CHECK = CHIP NOT M1_EXC_LOW ERR_WIN = DENSITY M1_CHECK CHIP_CHECK < M1_DN_1 WINDOW M1_DN_1_W STEP M1_DN_1_S INSIDE OF LAYER CHIP_M1 BACKUP [ AREA(M1_CHECK)/AREA(CHIP_CHECK) ] F = WITH WIDTH (ERR_WIN NOT M1_EXC_LOW) >= M1_DN_1_E DENSITY F M1_CHECK CHIP_CHECK < M1_DN_1 WINDOW M1_DN_1_W STEP M1_DN_1_S INSIDE OF LAYER CHIP_M1 BACKUP PRINT M1.DN.1.density [ !AREA(F)+AREA(M1_CHECK)/AREA(CHIP_CHECK) ] } 6. M1.DN.6 { @ Metal Desnsity >= 0.01. All condition-A, Condition-B, and Condition-C must be followed. @ (1) Condition-A: Metal density [window 80 um x 80 um, stepping 40 um] >= 0.01 @ (2) Condition-B: Maximum area of merged low density windows [window 10 um x 10 um, stepping 5 um < 0.01] <= 6400 um2, except merged low density windows width <= 30 um @ (3) Condition-C: Maximum area of merged low density windows [window 10 um x 10 um, stepping 5 um < 0.01] <= 18000 um2 @ 1. The following special regions are excluded while the density checking @ Chip corner triangle empty areas if sealring is added by tsmc. @ LOWMEDN @ 2. This rule is applied while the width of (checking window NOT above excluding region) >= 40 um for condition-A and >= 5 um for both condition-B/condition-C M1_CHECK = M1x NOT NEW_DEN_EXC CHIP_CHECK = CHIP NOT NEW_DEN_EXC // Condition-A ERR_WIN_A = DENSITY M1_CHECK CHIP_CHECK < M1_DN_6 WINDOW M1_DN_6_W_A STEP M1_DN_6_S_A INSIDE OF LAYER CHIP_M1 BACKUP [ AREA(M1_CHECK)/AREA(CHIP_CHECK) ] F_A = WITH WIDTH (ERR_WIN_A NOT NEW_DEN_EXC) >= M1_DN_6_E_A DENSITY F_A M1_CHECK CHIP_CHECK < M1_DN_6 WINDOW M1_DN_6_W_A STEP M1_DN_6_S_A INSIDE OF LAYER CHIP_M1 BACKUP PRINT M1.DN.6_A.density [ !AREA(F_A)+AREA(M1_CHECK)/AREA(CHIP_CHECK) ] // Condition-B ERR_WIN_B = DENSITY M1_CHECK CHIP_CHECK < M1_DN_6 WINDOW M1_DN_6_W_BC STEP M1_DN_6_S_BC INSIDE OF LAYER CHIP_M1 BACKUP [ AREA(M1_CHECK)/AREA(CHIP_CHECK) ] F_B = WITH WIDTH (ERR_WIN_B NOT NEW_DEN_EXC) >= M1_DN_6_E_BC A = DENSITY F_B M1_CHECK CHIP_CHECK < M1_DN_6 WINDOW M1_DN_6_W_BC STEP M1_DN_6_S_BC INSIDE OF LAYER CHIP_M1 BACKUP PRINT M1.DN.6_BC.density [ !AREA(F_B)+AREA(M1_CHECK)/AREA(CHIP_CHECK) ] B = AREA A > M1_DN_6_A_B C = SIZE B BY M1_DN_6_U/2 UNDEROVER B INTERACT C // Condition-C 7. Mx.DN. 7:M1_M2_M3 { @ It is not allowed to have local density < 5% of all 3 consecutive metal layer(M1,M2,M3) over any 30umx30um window (stepping 15um), i.e. it is allowed for either one of M1, M2, or M3 to have a local density >= 5 %. @ 1. The metal layers include M1/Mx and dummy metals @ 2. The following special regions are excluded while the density checking @ Chip corner triangle empty areas if sealring is added by tsmc. @ LOWMEDN @ 3. This rule is applied while the width of (checking window NOT above excluding region) >= 15 um M1_CHECK = M1x NOT NEW_DEN_EXC M2_CHECK = M2x NOT NEW_DEN_EXC M3_CHECK = M3x NOT NEW_DEN_EXC CHIP_CHECK = CHIP NOT NEW_DEN_EXC ERR_WIN = DENSITY M1_CHECK M2_CHECK M3_CHECK CHIP_CHECK >0 WINDOW M1_DN_7_W STEP M1_DN_7_S BACKUP INSIDE OF LAYER CHIP_M3 [ !~(M1_DN_7-AREA(M1_CHECK)/AREA(CHIP_CHECK))*!~(M1_DN_7-AREA(M2_CHECK)/AREA(CHIP_CHECK))*!~(M1_DN_7-AREA(M3_CHECK)/AREA(CHIP_CHECK)) ] F = WITH WIDTH (ERR_WIN NOT NEW_DEN_EXC) >= M1_DN_7_E DENSITY F M1_CHECK M2_CHECK M3_CHECK CHIP_CHECK >0 WINDOW M1_DN_7_W STEP M1_DN_7_S BACKUP INSIDE OF LAYER CHIP_M3 [ !!AREA(F)*!~(M1_DN_7-AREA(M1_CHECK)/AREA(CHIP_CHECK))*!~(M1_DN_7-AREA(M2_CHECK)/AREA(CHIP_CHECK))*!~(M1_DN_7-AREA(M3_CHECK)/AREA(CHIP_CHECK)) ] RDB Mx.DN.7:M1_M2_M3.density 8. BiB.R. 1 { @ PO_OD, CO_OD and CO_PO BiB patterns must inside CSR. @ PO_OD BiB pattern is formed by [OD ring + PO ring inside OD ring] @ CO_PO {CO_OD} BiB pattern is formed by [PO {OD} ring + CO ring inside PO {OD} ring (inner and outer)] (CSR_OD_HOLE NOT INTERACT CSRBIB1DMY) NOT INTERACT CSRBIB2DMY (CSR_OD_HOLE INTERACT CSRBIB1DMY) INTERACT CSRBIB2DMY A = CSR_OD_HOLE INTERACT CSRBIB1DMY A NOT ENCLOSE OD_BULK_BIB_COOD A NOT ENCLOSE PO_BULK_BIB_COOD B = CSR_OD_HOLE INTERACT CSRBIB2DMY B NOT ENCLOSE OD_BULK_BIB_POOD B NOT ENCLOSE PO_BULK_BIB_COOD CHIPx NOT INTERACT A == 2 CHIPx NOT INTERACT B == 2 } 9. SR.R. 1 { @ SEALRING layer (CAD layer: 162;0) and SEALRING_DB layer (CAD layer: 162;1) are Must if customers add seal ring by themselves. @ 162;0 is used to cover the outer seal ring (2um) and inner seal ring (6um); @ 162;1 is used to cover SLDB (3.5um duplicate). @ 162;2 is used to cover SEALRING, SLDB, and Assembly Isolation Region. @ SEALRING layer (162;0) , SEALRING_DB layer (162;1), and SEALRING_ALL layer (162;2) must exist. @ All the drawing of seal ring and SLDB structures must be inside of SEALRING (162;0) and SEALRING_DB (162;1). (except Mu) @ Please follow the CAD layers usage of 162;0, 162;1, and 162;2. @ Sealring related rules will not be checked without dummy layers. CHIP NOT INTERACT SEALRING_ORI SR_CO NOT (SEALRING_ORI OR SEALRING_DB) SR_VIA1 NOT (SEALRING_ORI OR SEALRING_DB) (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA1 (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA1_BAR SR_VIA2 NOT (SEALRING_ORI OR SEALRING_DB) (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA2 (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA2_BAR SR_VIA3 NOT (SEALRING_ORI OR SEALRING_DB) (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA3 (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA3_BAR SR_VIA4 NOT (SEALRING_ORI OR SEALRING_DB) (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA4 (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA4_BAR SR_VIA5 NOT (SEALRING_ORI OR SEALRING_DB) (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA5 (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA5_BAR SR_VIA6 NOT (SEALRING_ORI OR SEALRING_DB) (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA6 (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA6_BAR SR_VIA7 NOT (SEALRING_ORI OR SEALRING_DB) (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA7 (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA7_BAR SR_VIA8 NOT (SEALRING_ORI OR SEALRING_DB) (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA8 (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA8_BAR SR_VIA9 NOT (SEALRING_ORI OR SEALRING_DB) (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA9 (SEALRING_ORI OR SEALRING_DB) NOT INTERACT SR_VIA9_BAR CHIP NOT INTERACT SEALRING_DB CHIP NOT INTERACT SEALRING_ALL (SEALRING_ORI OR SEALRING_DB) NOT SEALRING_ALL } 10. CDU.R.1 { @ CDUDMY must be inside the assembly isolation beside seal ring. CDUDMY NOT INSIDE ISO_REGION ISO_REGION NOT INTERACT CDUDMY } 11. IND.DN. 3:M1 { @ M1/Mx/My/Mz/Mr metal density over the whole chip (include INDDMY) >= 20% DENSITY M1x CHIP < IND_DN_3 INSIDE OF LAYER CHIP_IND PRINT IND.DN.3:M1.density [ AREA(M1x)/AREA(CHIP) ] } 12. IND.DN. 7 { @ Maximum density of INDDMY in window 1600 um x 1600 um stepping 800 um <= 14 % DENSITY INDDMY_ALL CHIP > IND_DN_7 WINDOW IND_DN_7_W STEP IND_DN_7_S BACKUP INSIDE OF LAYER CHIPx PRINT IND.DN.7.density [AREA(INDDMY_ALL)/AREA(CHIP)] }
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