Synopsys Design Compiler Chip Synthesis Workshop, Student Guide Slides, 2019

AndyBrown

                               
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1. Introduction to Synthesis
2. Setup, Libraries, and Objects
3. Partitioning for Synthesis
4. Coding for Synthesis
5. Timing and Area
6. Environmental Attributes
7. Time and Load Budgeting
8. Timing Analsis
9. DC Tcl Introduction
10. Timing Revisited
11. Optimization
12. Compile Strategies
13. Compiling a Hierarchical Design
14. DC Tcl Procedures
15. Compiling a Large Design
16. Design Exloration
17. Synthesizing for Test
18. Conclusion

yuanpin318

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skahill

Thanks for sharing...

18812436116

Thanks!

icroad

多谢分享

Richard01

thanks

ic886

感谢分享

igolaps

thanks

tolerate_tao

感谢分享

tom0626

謝謝。感恩。