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发表于 2024-4-12 10:57:04
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本帖最后由 kk2009 于 2024-4-12 12:43 编辑
The purpose of this document is to help users get familiar with a standard cell Place and
Route (P&R) flow using VCP and new ART. The document shows the functionality of
the new ART standard cell router, which seamlessly integrates the NanoRoute router
into the Virtuoso design environment. The test case is a GPDK (cds_ff_mpt) standard
cell design.
It will start with a schematic and generate the layout from the source. Then, it will import
IO pins and boundary information from an existing layout as if it were done with the
Design Planner and Analysis tool. It will step through creating an interoperable row
region, which is compatible with Innovus, and then, it will do the power routing, followed
by placement of tap cells and standard cells.
It shows different ways to generate WSPs as well as routes without them, relying on
Innovus-created tracks. At that point, the design will be ready for routing, which is the
focus of the RAK.
It will also introduce GigaPlace integration through a SKILL API.
You may use this as an example to learn about the router and run further tests
(minimum prerequisite is RMSOA PDK and preferably abstracts).
Audience
This document is intended for circuit and layout designers using advanced-node PDKs
for their designs, as well as for CAD teams that support such design flows.
下面是文档中的图：
ART_StdCell_RAK_cds_ff_mpt.pdf
(7.48 MB, 下载次数: 38 )
ART_stdcell_RAK_cds_ff_mpt_05_01_2022.tar.gz
(5.54 MB, 下载次数: 24 )
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