求助virtuoso中functional生成symbol报错

ssmk

*WARNING* (TE-1312): Compilation errors or warnings have been detected in the HDL file for cellview 'TI_SAR_ADC verilog_14b functional'. To view the parse log for details, choose 'Parser Log File' from the 'View' menu.
*WARNING* (TE-4309): Extract failed for cellview 'TI_SAR_ADC verilog_14b functional'

打开Parser Log File后显示：
ncvlog(64): 15.20-p001: (c) Copyright 1995-2016 Cadence Design Systems, Inc.
UNDEFINE analogLib /opt/IC617/tools.lnx86/dfII/etc/cdslib/artist/analogLib
|
ncvlog: *F,DLCSYN (/opt/IC617/share/cdssetup/cds.lib,7): cds.lib Syntax error 'UNDEFINE analogLib /opt/IC617/tools.lnx86/dfII/etc/cdslib/artist/analogLib'.

uzljuljz

analogLib库在cds.lib里面定义成功了吗。

Jiny60377

11111

ssmk

uzljuljz 发表于 2024-4-7 09:15
analogLib库在cds.lib里面定义成功了吗。

定义了，在Library里能调用的

ssmk

已经解决了，是路劲下的analoglib库定义了两个

Vanty

请问是怎么解决的，没明白

JennniferHo

亲测也有可能是里面Verilog block name 和 cell name 不一致，也会报这个错误