PLL失锁了

ChenCH_FST

From the notes, it seems that there are stability and locking issues when the doubler is activated. These could be attributed to several factors including but not limited to the power supply noise, voltage levels, the loop filter design, charge pump currents, and VCO (Voltage-Controlled Oscillator) characteristics.

To address the questions:

The "doubler" may influence the VCO range, the phase noise (as it can potentially double the frequency noise), and the overall stability of the PLL. The "doubler" could be introducing additional noise or harmonics that affect the PLL's ability to lock to the desired frequency.

For debugging and simulation, you might consider:

Analyzing the power supply integrity, ensuring that the LDOs (Low Dropout Regulators) are providing clean and stable voltage levels.
Simulating the PLL with varying parameters in a software like Cadence or similar EDA (Electronic Design Automation) tools to observe the behavior changes with the doubler engaged.
Checking the loop filter design to make sure it's optimized for the new frequency range and noise profile when the doubler is active.
Observing the impact of changing the charge pump current and VCO gain (Kvco) in the simulation.
Measuring the phase noise with a spectrum analyzer to confirm the observations noted about the integral phase noise.
For simulations and practical troubleshooting, you'll need to use appropriate EDA tools and equipment to measure and adjust the PLL parameters. Additionally, the notes suggest that the system can lock by forcing a higher voltage to the div_ldo, which might point to an issue with the loop filter's charge pump or the VCO's tuning range/sensitivity.

xq19901211

   

wandola 发表于 2024-4-8 09:58
为什么div输出的占空比会影响你的性能？占空比是可调的么？

需要多给一些信息。简单的ldo scheamtic，vco ...

div占空比可调，不清楚为什么调占空比会影响相噪/锁定，并且仿真占空比最高的情况，实测反而无法锁定

doubler不打开，实测26M jitter有22ps
doubler delay通过调反相器vp/vn可调，另外doubler输出幅度是0dBm，jitter(7.5k-20M)是100ps,看上去噪声比较大,左右两边噪底抬高了,并且调节delay让doubler输出占空比变大后，jitter更差了，有1ns

现在只是TT，还没测最差corner
请大佬再指点一二

电子新手是也

是整数PLL吗？divider占空比可调，你用的是mmd结构吗？从mmd不同级输出的信号占空比是会不一样，而且相噪本身也是不一样的。

xq19901211

   

电子新手是也 发表于 2024-5-15 11:09
是整数PLL吗？divider占空比可调，你用的是mmd结构吗？从mmd不同级输出的信号占空比是会不一样，而且相噪本 ...

小数PLL，是PS counter,占空比不一样，相噪不一样，也不至于不锁定吧？

nanke

猜测是div_pfd以及pfd到cp的levelshit导致的问题。 环路正常需要你能检测到相位差，并根据相位差向LPF线性注入电流，以上电路在无电容ldo下效果差导致失去锁定。

nanke

   

nanke 发表于 2024-5-15 13:58
猜测是div_pfd以及pfd到cp的levelshit导致的问题。 环路正常需要你能检测到相位差，并根据相位差向LPF线性 ...

传统上，pll设计需要避免pfd死区，你这里有可能是类似问题。

nanke

楼主真惨，3个月还在搞这个问题。我比楼主更惨，啥基础没有就开始弄PLL，设计和测试得一塌糊涂，也没绩效。

电子新手是也

   

xq19901211 发表于 2024-5-15 13:45
小数PLL，是PS counter,占空比不一样，相噪不一样，也不至于不锁定吧？

输出占空比会变化很多吗？divider的输出可以测试吗？必须提高divider的电压才能锁定的话，也有可能是低电源电压的时候，divider本身分频出错了；或者占空比太小了，难以驱动下一级？

xq19901211

   

nanke 发表于 2024-5-15 13:58
猜测是div_pfd以及pfd到cp的levelshit导致的问题。 环路正常需要你能检测到相位差，并根据相位差向LPF线性 ...

"以上电路在无电容ldo下效果差"这句话没懂，你的意思是LDO的瞬态不行？

nanke

   

xq19901211 发表于 2024-5-15 16:05
"以上电路在无电容ldo下效果差"这句话没懂，你的意思是LDO的瞬态不行？

capless_ldo用于数字电路这种只在01切换瞬间有大电流的模块，瞬态响应很差。不同ldo结构表现也不一样。  既然外灌没问题，说明内部ldo有影响。