【南京cadence】招聘内推---超多假期！内推成功率高！

Lointain

• 内部员工内推成功率很高！反馈及时！
• 超多假期：15天年假 + 10天recharge day！
• 3+2 模式：每周二，周五固定居家办公！
• 不打卡，任务为导向，扁平管理，氛围很好！
• 现在有数字设计/验证，模拟设计，测试等岗位! 机会难得！详细职位介绍见2楼
  

需要内推的请将简历发送16653416526@126.com。 猎头勿扰！！！！

Lointain

1. Lead Design Engineer -Analog Design

职位描述
工作内容：

- 设计，模拟和验证10Gbps 以上的高速SerDes接口电路。

- 建立高速模拟电路模块的AMS模型和支持在数字集成中的IP联合验证。

- 定义IC 模块的性能指标和创建设计文档。

- 设计IC模块和指导layout布局。

- 芯片测试，性能验证和实验室调试。

- 团队分享设计经验和指导。

要求：

微电子，电路与系统等专业的硕士及以上学历，有扎实的电路分析理解能力。

有电磁场，传输线，螺旋电感，谐振电路的理论和实践经验，熟练使用Cadence工具。

能独立完成各种技术任务，能进行手工分析和验证，测试，量化自己的工作。

很好的沟通能力和团队合作能力。

2.Principal Design Engineer
Principal Design Engineer – Frontend

Location: Nanjing/Shanghai



Position Description:

Deliver/implement IC project.  The engineer should be able to act as a key team member with high efficiency and self driven.

Specific duties include:

Frontend experienced designer for successful IP/subsystem/testchip tape-out.
Strong self driven, independent problem solving, good communication and teamwork skills.
Proficiency in design from SPEC to RTL , simulation, synthesis, STA and micro-architecture bring-up, testing.
Proficiency in SoC and ASIC design flow and sign-off, especially front-end.


Position Requirements:

Master degree with 5+ years as an experienced SoC front-end design engineer.
Expertise in micro-architecture bring-up and Verilog RTL digital design in SoC and ASIC chips.
Experienced in using STA, DFT and formal check tools
Experienced in successful tape-out of SoC/ASIC chips
Good knowledge and understanding on high performance / low power SOC and ASIC design, verification and power/timing

3.Principal Verification Engineer

职位描述
Principal Design Engineer – Verification

Location: Nanjing/Shanghai



Position Description:

Lead project verification. The engineer should be good at teamwork and able to help team development.

Specific duties include:

Responsible for verification plan define based on IP design SPEC.
Lead verification team to achieve the coverage driven verification goals.
Verification Test-Bench maintain and development.
Deep understanding on ASIC verification flow, responsible for milestone delivery check


Position Requirements:

Master degree with 4+ years or bachelor with 7+ years as an experienced digital IC verification.
Experienced in successful tape-out of ASIC chips
Familiar to UVM test-bench architecture and experienced on test-bench development.
Self-motivation with communication skills (spoken and written English and Mandarin)
Be familiar to the coding of SV, Perl/Python, Makefile
Experience on leading verification project is ++.

4. Sr Principal Design Engineer
Location: Nanjing/Shanghai



Position Description:

Deliver/implement IC project. The engineer should be able to act as an expert or leader on ASIC/SoC front end design.

Specific duties include:

Frontend technical expert and team leader for successful IP/subsystem/testchip tape-out
Strong self driven, independent problem solving, technical decision making, good communication and teamwork skills.
Proficiency in design from complex protocol analysis to spec and RTL coding, simulation, synthesis, STA and micro-architecture bring-up, testing.
Proficiency in SoC and ASIC design flow and sign-off, especially front-end.


Position Requirements:

Master degree with 7+ years as a senior SoC front-end design technical leader.
Expertise in micro-architecture bring-up and Verilog RTL digital design in SoC and ASIC chips in 28nm deep submicron technologies and beyond
Experienced in using STA, DFT and formal check tools
Experienced in successful tape-out of SoC/ASIC chips
Good knowledge and understanding on high performance / low power SOC and ASIC design, verification and power/timing
Self-motivation with communication skills (spoken and written English and Mandarin)

5.Lead Design Engineer – Verification

Location: Nanjing/Shanghai



Position Description:

Specific duties include:

Responsible for verification plan define based on IP design SPEC.
Lead verification team to achieve the coverage driven verification goals.
Verification Test-Bench maintain and development.
Deep understanding on ASIC verification flow, responsible for milestone delivery check


Position Requirements:

Master degree with 2+ years or bachelor with 4+ years as an experienced digital IC verification.
Experienced in successful tape-out of ASIC chips
Familiar to UVM test-bench architecture and experienced on test-bench development.
Self-motivation with communication skills (spoken and written English and Mandarin)
Experienced in coding of SV, Perl/Python, Makefile

6.Lead Design Engineer (PCB设计/SIPI仿真）
Design Engineer (PCB设计/SIPI仿真)

工作地点：南京



Job Description:

负责Highspeed Serdes 和 DDR IP 测试评估版的原理图和PCB 设计；

独立完成测试评估版及package的SI/PI 仿真；

协同设计者解决IP验证测试遇到的问题



Requirements:

微电子, 电子工程或计算机相关专业，本科以上学历，至少3年PCB设计经验

扎实的数字和模拟电路基础知识，有良好的硬件设计基础，熟练使用示波器，BERT 及逻辑分析仪

熟悉Python/C等脚本语言优先

熟悉硬件设计和SI/PI经验优先

较强的中英文沟通写作能力, 较强的问题分析以及团队合作能力

7. Lead Product Engineer (DDR IP)
Job Summary:

Join a growing and dynamic IP team and help lead the development of best in class digital and mixed signal IP products.  This is a tremendous opportunity to work with an experienced team focusing on development of high-performance IP related to DDR DDR4/DDR5/LPDDR4/LPDDR5.



The role will be a key member of technical staff in an organization responsible for IP activities including but not limited to Pre-sales engagement with potential customers, Pre-Silicon integration and Post silicon bring-up and test support for the customers.

This candidate will be the primary interface between customer and CDNS R&D team. Candidate should possess strong communication skills with ability to manage multiple priorities on day-to-day basis. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication of status, must have attributes in this role.



Primary Responsibilities:

Responsible for supporting integration / customization / post silicon bring up of CDNS DDR IP subsystems.
Analyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers.
Support DDR PHY and controller SOC integration reviews, and integration questions.
Perform RTL and gate level simulations to verify functionality.
Assist customers with gate level simulations and timing closure.
Participate in development of CDNS documentations and checklists for customers.
Support post silicon bringup and deployment activities by our customers.
Enhance customer experience by providing prompt updates to customers.


Position Requirements:               

M.S. Electrical/Computer Engineering (or similar degree) with 3+ years of overall experience
Experience working with DDR4/5, LPDDR4/5 IP.
Verilog RTL design and gate level verification experience.
Synthesis and STA experience, back-end experience is a plus.
Familiarity with industry standard DFT flows and test methodologies.
Familiarity with package and board design.
Ability to read schematics and participate in SI/PI reviews for customer board/package implementation.


Preferred Qualifications

Experience with DDR PHY and DSP based architectures.

8. Principal Design Engineer (Emulation/FPGA prototyping)
Job Summary:

This is a unique opportunity to join the rapidly growing System Emulation team in the IP R&D Group at Cadence Design Systems. This is a tremendous opportunity to work with an experienced team focusing on development of high-performance IP related to protocols such as PCIe, CXL, UCIe, USB, DPHY and Ethernet PHYs.

We are looking for a Lead Design Engineer who will be responsible for developing palladium verification platform for cadence PHY with Controller IPs and developing subsystem-based FPGA prototyping design for all Cadence IPs.

This is a hands-on technical position.  The candidate must have experience successfully integrating/designing/prototyping high speed IP in FPGA/Emulation Platform.



Requirements:

Should have 5+ years of experience in FPGA Prototyping/Emulation.
Hand on experience on any FPGA/Emulation tool flow.
Should have System Verilog/Verilog based coding.
Experience in Writing C-based test cases.
Experience in any high-speed IP (PCIE/USB/Ethernet/DPHY).
Experience on system bus protocols USB3/PCIe, AXI, APB is desirable.
Working experience on any Cadence Simulator tool (Xcelium/Incisive) and Palladium Emulation
Working knowledge of Python/TCL, Makefile scripting languages.
Good communication skills.

9.Design Engineer 芯片验证测试工程师
Job Description:

参与Highspeed Serdes 和 DDR IP 测试评估版的设计和开发；

负责PCIE, USB, 10G-KR Serdes IP 一致性测试；

负责DDR4/LPDDR4X/DDR5/LPDDR5 IP 一致性测试。

依据实际的测试方案，编写自动化测试脚本

协同设计者解决IP验证测试遇到的问题



Requirements:

微电子, 电子工程或计算机相关专业，全日制本科以上学历

扎实的数字和模拟电路基础知识

有一定的硬件设计基础，熟练使用示波器，BERT 及逻辑分析仪

熟悉Python/C等脚本语言

较强的中英文沟通写作能力, 较强的问题分析以及团队合作能力

Lointain

Lead Design Engineer – Verification
Location: Nanjing/Shanghai   
Position Description:   
Specific duties include:  

• Responsible for verification plan define based on IP design SPEC.
• Lead verification team to achieve the coverage driven verification goals.
• Verification Test-Bench maintain and development. Deep understanding on ASIC verification flow, responsible for milestone delivery check
  

Position Requirements:  

• Master degree with 2+ years or bachelor with 4+ years as an experienced digital IC verification.
• Experienced in successful tape-out of ASIC chips
• Familiar to UVM test-bench architecture and experienced on test-bench development.
• Self-motivation with communication skills (spoken and written English and Mandarin)
• Experienced in coding of SV, Perl/Python, Makefile
  

Principal Design Engineer

Principal Design Engineer – Frontend

Location: Nanjing/Shanghai

Position Description:

Deliver/implement IC project.  The engineer should be able to act as a key team member with high efficiency and self driven.

Specific duties include:

• Frontend experienced designer for successful IP/subsystem/testchip tape-out.
• Strong self driven, independent problem solving, good communication and teamwork skills.
• Proficiency in design from SPEC to RTL , simulation, synthesis, STA and micro-architecture bring-up, testing.
• Proficiency in SoC and ASIC design flow and sign-off, especially front-end.
  

Position Requirements:

• Master degree with 5+ years as an experienced SoC front-end design engineer.
• Expertise in micro-architecture bring-up and Verilog RTL digital design in SoC and ASIC chips.
• Experienced in using STA, DFT and formal check tools
• Experienced in successful tape-out of SoC/ASIC chips
• Good knowledge and understanding on high performance / low power SOC and ASIC design, verification and power/timing
  

Principal Verification Engineer

Principal Design Engineer – Verification

Location: Nanjing/Shanghai

Position Description:

Lead project verification. The engineer should be good at teamwork and able to help team development.

Specific duties include:

• Responsible for verification plan define based on IP design SPEC.
• Lead verification team to achieve the coverage driven verification goals.
• Verification Test-Bench maintain and development.
• Deep understanding on ASIC verification flow, responsible for milestone delivery check
  

Position Requirements:

• Master degree with 4+ years or bachelor with 7+ years as an experienced digital IC verification.
• Experienced in successful tape-out of ASIC chips
• Familiar to UVM test-bench architecture and experienced on test-bench development.
• Self-motivation with communication skills (spoken and written English and Mandarin)
• Be familiar to the coding of SV, Perl/Python, Makefile
• Experience on leading verification project is ++.
  

Sr Principal Design Engineer

Sr Principal Design Engineer – Frontend

Location: Nanjing/Shanghai

Position Description:

Deliver/implement IC project. The engineer should be able to act as an expert or leader on ASIC/SoC front end design.

Specific duties include:

• Frontend technical expert and team leader for successful IP/subsystem/testchip tape-out
• Strong self driven, independent problem solving, technical decision making, good communication and teamwork skills.
• Proficiency in design from complex protocol analysis to spec and RTL coding, simulation, synthesis, STA and micro-architecture bring-up, testing.
• Proficiency in SoC and ASIC design flow and sign-off, especially front-end.
  

Position Requirements:

• Master degree with 7+ years as a senior SoC front-end design technical leader.
• Expertise in micro-architecture bring-up and Verilog RTL digital design in SoC and ASIC chips in 28nm deep submicron technologies and beyond
• Experienced in using STA, DFT and formal check tools
• Experienced in successful tape-out of SoC/ASIC chips
• Good knowledge and understanding on high performance / low power SOC and ASIC design, verification and power/timing
• Self-motivation with communication skills (spoken and written English and Mandarin)
  

jiangnaner

不错

Lointain

这次招聘岗位算是挺多的，机会难得，最快当天就可以给反馈

Lointain

要求工作至少2年以上的研究生