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lingqinzi

根据dwc_ddr54_phy_v2_tsmc6ff18/1.30a package dwc_ddr54_phy_ig.pdf 中section 9.4.2 Special Checks的描述,
1.        Checklist 9-9中提到了需要review PLL jitter spreadsheet中expected DfiClk latency与SOC PLL characteristics，所以请帮忙提供一下PLL jitter spreadsheet文档。或是由我们提供需要review的SOC PLL参数（DfiClk由SOC PLL提供），请Synopsys帮我们review。
2.        Checklist 9-10中提到了DfiClk从PHY port到macro port的clock latency会影响read/write FIFO，需要review programming的system latency特别是要review programming ARdPtrInitVal的。我们需要review要用到的具体criteria，以及是否需要加上SOC PLL到PHY DfiClk port的latency以及programming时SOC bus上的latency。

According to the Section 9.4.2 Special Checks in dwc_ddr54_phy_ig.pdf file in dwc_ddr54_phy_v2_tsmc6ff18/1.30a PHY package,
1.        On Checklist 9-9, it says that the noise, jitter and latency from the source PLL will affect the performance on the DRAM CK. Review the functional impact of the expected DfiClk latency and SoC PLL characteristics in the PLL jitter spreadsheet to ensure the correct performance. Please help to provide the PLL jitter spreadsheet, or we can provide the SOC PLL characteristics (since DfiClk provided by SOC PLL) and Synopsys will help us review it.
2.        On Checklist 9-10, the DfiClk clock tree latency from PHY ports to hard-macro DfiClk pins affects the read and write FIFO. Review the programming of the system latency and specifically the programming of the ARdPtrInitVal as described in the PUB Databook [section ARdPtrInitVal Impacts From Construction Skews]. So, we want to know the detailed criteria for review. And whether we need add the clock latency from SOC PLL to PHY DfiClk port and the SOC bus latency during programming.

lingqinzi

麻烦管理员帮忙删帖。错误发出来的。