layout LVS问题

ilku · 发表于 2024-1-8 16:19:41

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各位大佬，我最近在画一个版图，底层小模块DRC LVS都没有问题，顶层出现了一点问题，显示底层小模块的电阻有问题，不知道该怎么解决，各位大佬能帮忙看看吗，LVS report 如下：

CELL COMPARISON RESULTS ( TOP LEVEL )

               # #       #####################
               # #       #                #
                  #          #    INCORRECT    #
               # #       #                #
               # #       #####################

  Error: Different numbers of nets (see below).
  Error: Different numbers of instances (see below).
  Error: Connectivity errors.
  Error: Property errors.
  Warning:  Unbalanced smashed mosfets were matched.
  Warning:  Ambiguity points were found and resolved arbitrarily.

layout CELL NAME:       LDO
SOURCE CELL NAME:       LDO

--------------------------------------------------------------------------------------------------------------

INITIAL NUMBERS OF OBJECTS
--------------------------

            Layout Source       Component Type
            ------ ------       --------------
Ports:          109    109

Nets:          901    892 *

Instances:       720    644 * MN (4 pins)
               3760    3640 * MP (4 pins)
                  25       25       Q (3 pins)
               902    902       C (3 pins)
               108    108       R (2 pins): (p n)
               683    667 * R (3 pins): (p n) sub
               1922       0 * D (2 pins)
            ------ ------
Total Inst:    8120    5986

NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------

            Layout Source       Component Type
            ------ ------       --------------
Ports:          109    109

Nets:          763    755 *