DC综合dct模式下各种warning的出现原因及解决方法

Zwy303301659

（1）Warning: There is no defined clock in the design. (PWR-80)
（2）Warning: Design has unannotated black box outputs. (PWR-428)
（3）signed to unsigned assignment occurs. (VER-318)
（4)  Warning: ContactCode 'CONT1' is missing the attribute 'unitMinResistance'. (line 788) (TFCHK-014)
（5）Warning: Layer 'METAL1' has a pitch 0.56 that does not match the recommended wire-to-via pitch 0.535 or 0.485. (TFCHK-049)
（6）Warning: The 'AFHCINX45wwfcwwwwd0jh3qy' cell in the 'xx/milkyway/stdcell/sage-x_tsmc_cl018g_rvt' physical library does not have corresponding logical cell description. (PSYN-025)
（7）Warning: The compile_timing_high_effort variable is a hidden variable. When setting this variable to true with the compile_ultra command, the tool performs higher effort optimizations, resulting in a longer runtime than running compile_ultra without the variable. Use compile_ultra without the variable as the default optimization strategy, and enable the variable only when your design requires further timing optimization.

（8）Warning: Layer 'METAL1' has a pitch 0.56 that does not match the recommended wire-to-via pitch 0.535 or 0.485. (TFCHK-049)
（9）Warning: Disabling timing arc between pins 'CK' and 'Q' on cell 'u_dc/req_csm_sel_reg[0]' to break a timing loop. (OPT-314)
（10）Warning: The trip points for the library named USERLIB differ from those in the library named sage-x_tsmc_cl018g_rvt_ss_1p62v_125c. (TIM-164)
（11）Warning: Net 'u_img/sg2pack_entry_end[0]' already has '  0.00 (max)' for annotated capacitance. '  0.00 (max)' is discarded. (OPT-806)
（12）Warning: Placer unable to satisfy constraints on macro cell u_RAMF_256X64. (PSYN-362)
87%...93%...100% done.
（13）

zero_0

man PWR-80