vivado如何连接两个 6x的Aurora

TUJzzz

vivado版本 2018.3

aurora核：64b66b 11.2
问题描述：
一个12x的aurora 使用了三个gt_common资源，我想把他拆分成两个6x的aurora，6x的aurora（共享逻辑放在外部）所生成的example_design中，每个gt_common模块使用了两个gt_common原语，所以我换成了一个12x_aurora生成的gt_common_12x（内部模块使用三个gt_common原语）然后将其中一个gt_common原语的输出连接到两个aurora_6x上，或者是三个4x_aurora生成的gt_comon_4x，然后把其中一个gt_common_4x连接到两个aurora_6x上。但是始终无法成功生成bit，主要错误类型有下面三个：
1.[Place 30-512] Clock region assignment has failed. Clock buffer 'design_5_wrapper_inst/design_5_i/aurora6x_64b66b_5_CL_0/inst/IBUFDS_GTXE2_CLK1' (IBUFDS_GTE2) is placed at site IBUFDS_GTE2_X1Y2 in CLOCKREGION_X1Y1. Its loads need to be placed in the area enclosed by clock regions CLOCKREGION_X1Y1 and CLOCKREGION_X1Y1. One of its loads 'design_5_wrapper_inst/design_5_i/aurora_2_6x/aurora6x_64b66b_5_gt_0/inst/gthe2_common_lane1_i' (GTHE2_COMMON) is placed in site GTHE2_COMMON_X0Y9 in CLOCKREGION_X0Y9 which is outside the permissible area.

2.[DRC RTSTAT-1] Unrouted nets: 8 net(s) are unrouted. The problem bus(es) and/or net(s) are AURORA_8_6X_wrapper_inst/AURORA_8_6X_i/aurora_2_6x/aurora6x_64b66b_5_gt_1/inst/gt_qpllclk_quad1_out, AURORA_8_6X_wrapper_inst/AURORA_8_6X_i/aurora_2_6x1/aurora6x_64b66b_5_gt_1/inst/gt_qpllclk_quad1_out, AURORA_8_6X_wrapper_inst/AURORA_8_6X_i/aurora_2_6x2/aurora6x_64b66b_5_gt_1/inst/gt_qpllclk_quad1_out, AURORA_8_6X_wrapper_inst/AURORA_8_6X_i/aurora_2_6x3/aurora6x_64b66b_5_gt_1/inst/gt_qpllclk_quad1_out, AURORA_8_6X_wrapper_inst/AURORA_8_6X_i/aurora_2_6x/aurora6x_64b66b_5_gt_1/inst/gt_qpllrefclk_quad1_out, AURORA_8_6X_wrapper_inst/AURORA_8_6X_i/aurora_2_6x1/aurora6x_64b66b_5_gt_1/inst/gt_qpllrefclk_quad1_out, AURORA_8_6X_wrapper_inst/AURORA_8_6X_i/aurora_2_6x2/aurora6x_64b66b_5_gt_1/inst/gt_qpllrefclk_quad1_out, and AURORA_8_6X_wrapper_inst/AURORA_8_6X_i/aurora_2_6x3/aurora6x_64b66b_5_gt_1/inst/gt_qpllrefclk_quad1_out.

3.[Place 30-143] Sub-optimal placement for an IBUFDS / GT component pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
        < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_2_wrapper_inst/design_2_i/aurora12x_64b66b_0_C_0/inst/refclk1_in] >

        design_2_wrapper_inst/design_2_i/aurora12x_64b66b_0_C_0/inst/IBUFDS_GTXE2_CLK1 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X1Y2
         design_2_wrapper_inst/design_2_i/aurora12x_64b66b_1_g_0/inst/gthe2_common_i (GTHE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y0
         design_2_wrapper_inst/design_2_i/aurora12x_64b66b_1_g_0/inst/gthe2_common_lane1_i (GTHE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y1
         design_2_wrapper_inst/design_2_i/aurora12x_64b66b_1_g_0/inst/gthe2_common_lane2_i (GTHE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y2
         design_2_wrapper_inst/design_2_i/aurora12x_64b66b_1_g_1/inst/gthe2_common_i (GTHE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y3
         design_2_wrapper_inst/design_2_i/aurora12x_64b66b_1_g_1/inst/gthe2_common_lane1_i (GTHE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y4
         design_2_wrapper_inst/design_2_i/aurora12x_64b66b_1_g_1/inst/gthe2_common_lane2_i (GTHE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y5

        The above error could possibly be related to other connected instances. Following is a list of
        all the related clock rules and their respective instances.

        Clock Rule: rule_gthcommon_gthchannel
        Status: PASS
        Rule Description: A GTHCommon driving a GTHChannel must both be in the same clock region
         design_2_wrapper_inst/design_2_i/aurora12x_64b66b_1_g_0/inst/gthe2_common_i (GTHE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y0
         design_2_wrapper_inst/design_2_i/aurora_64b66b_0/inst/design_2_aurora_64b66b_0_0_wrapper_i/design_2_aurora_64b66b_0_0_multi_gt_i/design_2_aurora_64b66b_0_0_gt_inst/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y0
         design_2_wrapper_inst/design_2_i/aurora_64b66b_0/inst/design_2_aurora_64b66b_0_0_wrapper_i/design_2_aurora_64b66b_0_0_multi_gt_i/design_2_aurora_64b66b_0_0_gt_inst_lane1/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y1
         design_2_wrapper_inst/design_2_i/aurora_64b66b_0/inst/design_2_aurora_64b66b_0_0_wrapper_i/design_2_aurora_64b66b_0_0_multi_gt_i/design_2_aurora_64b66b_0_0_gt_inst_lane2/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y2
         design_2_wrapper_inst/design_2_i/aurora_64b66b_0/inst/design_2_aurora_64b66b_0_0_wrapper_i/design_2_aurora_64b66b_0_0_multi_gt_i/design_2_aurora_64b66b_0_0_gt_inst_lane3/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y3

        Clock Rule: rule_gthcommon_gthchannel
        Status: PASS
        Rule Description: A GTHCommon driving a GTHChannel must both be in the same clock region
         design_2_wrapper_inst/design_2_i/aurora12x_64b66b_1_g_0/inst/gthe2_common_lane1_i (GTHE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y1
         design_2_wrapper_inst/design_2_i/aurora_64b66b_0/inst/design_2_aurora_64b66b_0_0_wrapper_i/design_2_aurora_64b66b_0_0_multi_gt_i/design_2_aurora_64b66b_0_0_gt_inst_lane4/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y4
         design_2_wrapper_inst/design_2_i/aurora_64b66b_0/inst/design_2_aurora_64b66b_0_0_wrapper_i/design_2_aurora_64b66b_0_0_multi_gt_i/design_2_aurora_64b66b_0_0_gt_inst_lane5/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y5
         design_2_wrapper_inst/design_2_i/aurora_64b66b_0/inst/design_2_aurora_64b66b_0_0_wrapper_i/design_2_aurora_64b66b_0_0_multi_gt_i/design_2_aurora_64b66b_0_0_gt_inst_lane6/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y6
         design_2_wrapper_inst/design_2_i/aurora_64b66b_0/inst/design_2_aurora_64b66b_0_0_wrapper_i/design_2_aurora_64b66b_0_0_multi_gt_i/design_2_aurora_64b66b_0_0_gt_inst_lane7/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y7

        Clock Rule: rule_gthcommon_gthchannel
        Status: PASS
        Rule Description: A GTHCommon driving a GTHChannel must both be in the same clock region
         design_2_wrapper_inst/design_2_i/aurora12x_64b66b_1_g_0/inst/gthe2_common_lane2_i (GTHE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y2
         design_2_wrapper_inst/design_2_i/aurora_64b66b_0/inst/design_2_aurora_64b66b_0_0_wrapper_i/design_2_aurora_64b66b_0_0_multi_gt_i/design_2_aurora_64b66b_0_0_gt_inst_lane10/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y10
         design_2_wrapper_inst/design_2_i/aurora_64b66b_0/inst/design_2_aurora_64b66b_0_0_wrapper_i/design_2_aurora_64b66b_0_0_multi_gt_i/design_2_aurora_64b66b_0_0_gt_inst_lane11/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y11
         design_2_wrapper_inst/design_2_i/aurora_64b66b_0/inst/design_2_aurora_64b66b_0_0_wrapper_i/design_2_aurora_64b66b_0_0_multi_gt_i/design_2_aurora_64b66b_0_0_gt_inst_lane8/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y8
         design_2_wrapper_inst/design_2_i/aurora_64b66b_0/inst/design_2_aurora_64b66b_0_0_wrapper_i/design_2_aurora_64b66b_0_0_multi_gt_i/design_2_aurora_64b66b_0_0_gt_inst_lane9/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y9

        Clock Rule: rule_gthcommon_gthchannel
        Status: PASS
        Rule Description: A GTHCommon driving a GTHChannel must both be in the same clock region
         design_2_wrapper_inst/design_2_i/aurora12x_64b66b_1_g_1/inst/gthe2_common_i (GTHE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y3
         design_2_wrapper_inst/design_2_i/aurora_64b66b_1/inst/design_2_aurora_64b66b_0_2_wrapper_i/design_2_aurora_64b66b_0_2_multi_gt_i/design_2_aurora_64b66b_0_2_gt_inst/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y12
         design_2_wrapper_inst/design_2_i/aurora_64b66b_1/inst/design_2_aurora_64b66b_0_2_wrapper_i/design_2_aurora_64b66b_0_2_multi_gt_i/design_2_aurora_64b66b_0_2_gt_inst_lane1/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y13
         design_2_wrapper_inst/design_2_i/aurora_64b66b_1/inst/design_2_aurora_64b66b_0_2_wrapper_i/design_2_aurora_64b66b_0_2_multi_gt_i/design_2_aurora_64b66b_0_2_gt_inst_lane2/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y14
         design_2_wrapper_inst/design_2_i/aurora_64b66b_1/inst/design_2_aurora_64b66b_0_2_wrapper_i/design_2_aurora_64b66b_0_2_multi_gt_i/design_2_aurora_64b66b_0_2_gt_inst_lane3/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y15

        Clock Rule: rule_gthcommon_gthchannel
        Status: PASS
        Rule Description: A GTHCommon driving a GTHChannel must both be in the same clock region
         design_2_wrapper_inst/design_2_i/aurora12x_64b66b_1_g_1/inst/gthe2_common_lane1_i (GTHE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y4
         design_2_wrapper_inst/design_2_i/aurora_64b66b_1/inst/design_2_aurora_64b66b_0_2_wrapper_i/design_2_aurora_64b66b_0_2_multi_gt_i/design_2_aurora_64b66b_0_2_gt_inst_lane4/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y16
         design_2_wrapper_inst/design_2_i/aurora_64b66b_1/inst/design_2_aurora_64b66b_0_2_wrapper_i/design_2_aurora_64b66b_0_2_multi_gt_i/design_2_aurora_64b66b_0_2_gt_inst_lane5/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y17
         design_2_wrapper_inst/design_2_i/aurora_64b66b_1/inst/design_2_aurora_64b66b_0_2_wrapper_i/design_2_aurora_64b66b_0_2_multi_gt_i/design_2_aurora_64b66b_0_2_gt_inst_lane6/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y18
         design_2_wrapper_inst/design_2_i/aurora_64b66b_1/inst/design_2_aurora_64b66b_0_2_wrapper_i/design_2_aurora_64b66b_0_2_multi_gt_i/design_2_aurora_64b66b_0_2_gt_inst_lane7/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y19

        Clock Rule: rule_gthcommon_gthchannel
        Status: PASS
        Rule Description: A GTHCommon driving a GTHChannel must both be in the same clock region
         design_2_wrapper_inst/design_2_i/aurora12x_64b66b_1_g_1/inst/gthe2_common_lane2_i (GTHE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y5
         design_2_wrapper_inst/design_2_i/aurora_64b66b_1/inst/design_2_aurora_64b66b_0_2_wrapper_i/design_2_aurora_64b66b_0_2_multi_gt_i/design_2_aurora_64b66b_0_2_gt_inst_lane10/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y22
         design_2_wrapper_inst/design_2_i/aurora_64b66b_1/inst/design_2_aurora_64b66b_0_2_wrapper_i/design_2_aurora_64b66b_0_2_multi_gt_i/design_2_aurora_64b66b_0_2_gt_inst_lane11/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y23
         design_2_wrapper_inst/design_2_i/aurora_64b66b_1/inst/design_2_aurora_64b66b_0_2_wrapper_i/design_2_aurora_64b66b_0_2_multi_gt_i/design_2_aurora_64b66b_0_2_gt_inst_lane8/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y20
         design_2_wrapper_inst/design_2_i/aurora_64b66b_1/inst/design_2_aurora_64b66b_0_2_wrapper_i/design_2_aurora_64b66b_0_2_multi_gt_i/design_2_aurora_64b66b_0_2_gt_inst_lane9/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y21

        Clock Rule: rule_gt_bufg
        Status: PASS
        Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device
         design_2_wrapper_inst/design_2_i/aurora_64b66b_0/inst/design_2_aurora_64b66b_0_0_wrapper_i/design_2_aurora_64b66b_0_0_multi_gt_i/design_2_aurora_64b66b_0_0_gt_inst_lane6/gthe2_i (GTHE2_CHANNEL.RXOUTCLK) is locked to GTHE2_CHANNEL_X1Y6
         design_2_wrapper_inst/design_2_i/aurora_64b66b_0/inst/design_2_aurora_64b66b_0_0_wrapper_i/rxrecclk_bufg_i (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

        Clock Rule: rule_gt_bufg
        Status: PASS
        Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device
         design_2_wrapper_inst/design_2_i/aurora_64b66b_1/inst/design_2_aurora_64b66b_0_2_wrapper_i/design_2_aurora_64b66b_0_2_multi_gt_i/design_2_aurora_64b66b_0_2_gt_inst_lane6/gthe2_i (GTHE2_CHANNEL.RXOUTCLK) is locked to GTHE2_CHANNEL_X1Y18
         and design_2_wrapper_inst/design_2_i/aurora_64b66b_1/inst/design_2_aurora_64b66b_0_2_wrapper_i/rxrecclk_bufg_i (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y2


[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances


BD连接如下图所示：

使用三个gt_common_4x

使用两个个gt_common_6x（这样gt_common原语的资源会不够）