★新书上架—低功耗设计☆Closing the Power Gap Between ASIC & Custom

rfjungle

thanks!!!

retiming

不错，支持！！！

bobo1982

谢谢楼主，学习一下

sq143

有了，学习 1# benemale

lmz05

1# benemale

mscyc0909

CONTENTS
1. Introduction 1
David Chinnery, Kurt Keutzer
1.1 Definitions: ASIC and custom.........................................................1
1.2 What is a standard cell ASIC methodology?...................................3
1.3 Who should care about this book?...................................................6
1.4 Organization of the rest of the book ................................................8
1.5 What’s not in this book....................................................................9
CONTRIBUTING FACTORS
2. Overview of the Factors Affecting the Power Consumption 11
David Chinnery, Kurt Keutzer
2.1 Introduction....................................................................................11
2.2 Process technology independent FO4 delay metric ......................12
2.3 Components of power consumption..............................................14
2.4 ASIC and custom power comparison ............................................15
2.5 Factors contributing to ASICs being higher power.......................19
2.6 Summary........................................................................................47
3. Pipelining to Reduce the Power 55
David Chinnery, Kurt Keutzer
3.1 Introduction....................................................................................57
3.2 Pipelining overheads......................................................................61
3.3 Pipelining power and delay model ................................................67
3.4 ASIC versus custom pipelining .....................................................74
3.5 Other factors affecting the power gap ...........................................81
3.6 Other factors affecting the minimum energy per operation ..........81
3.7 Summary........................................................................................84
4. Voltage Scaling 89
David Chinnery, Kurt Keutzer
4.1 Introduction....................................................................................89
4.2 Delay..............................................................................................90
4.3 Switching power ............................................................................94
4.4 Short circuit power ........................................................................95
4.5 Leakage power...............................................................................97
4.6 0.13um data for total power...........................................................99
4.7 Summary......................................................................................104
DESIGN TECHNIQUES
5. Methodology to Optimize Energy of Computation for SOCs 107
Jagesh Sanghavi, Eliot Gerstner
5.1 Introduction..................................................................................107
5.2 Problem definition and solution approach...................................109
5.3 Optimization methodology ..........................................................110
5.4 Experimental results ....................................................................113
5.5 Summary......................................................................................119
6. Linear Programming for Gate Sizing 121
David Chinnery, Kurt Keutzer
6.1 Introduction..................................................................................121
6.2 Overview of TILOS gate sizing...................................................124
6.3 Linear programming formulation ................................................126
6.4 Optimization flow........................................................................137
6.5 Comparison of gate sizing results................................................140
6.6 Computational runtime ................................................................143
6.7 Summary......................................................................................147
7. Linear Programming for Multi-Vth and Multi-Vdd Assignment 151
David Chinnery, Kurt Keutzer
7.1 Introduction..................................................................................151
7.2 Voltage level restoration for multi-Vdd ......................................155
7.3 Previous multi-Vdd and multi-Vth optimization research ..........156
7.4 Optimizing with multiple supply and threshold voltages............160
7.5 Comparison of multi-Vdd and multi-Vth results ........................167
7.6 Analysis of power savings with multi-Vth and multi-Vdd .........171
7.7 Computational runtimes with multi-Vdd and multi-Vth.............185
7.8 Summary......................................................................................186
8. Power Optimization using Multiple Supply Voltages 189
Sarvesh Kulkarni, Ashish Srivastava,
Dennis Sylvester, David Blaauw
8.1 Introduction..................................................................................189
8.2 Overview of CVS and ECVS ......................................................192
8.3
8.4 Power savings with CVS and GECVS ........................................199
8.5 Gate sizing and dual-Vth assignment ..........................................201
8.6 Power savings with VVS and GVS.............................................211
8.7 Summary......................................................................................214
9. Placement for Power Optimization 219
Ameya R. Agnihotri, Satoshi Ono, Patrick H. Madden
9.1 Introduction..................................................................................219
9.2 Placement basics..........................................................................221
9.3 Physical synthesis ........................................................................226
9.4 Multiple supply voltage placement .............................................239
9.5 State of the art..............................................................................242
9.6 Summary......................................................................................246
10. Power Gating Design Automation 251
Jerry Frenkil, Srini Venkatraman
10.1 Introduction..................................................................................251
10.2 Leakage control techniques .........................................................252
10.3 Power gating design issues ..........................................................255
10.4 Coolpower design automation .....................................................262
10.5 Application flows.........................................................................269
10.6 Results..........................................................................................272
10.7 Future work..................................................................................277
10.8 Summary......................................................................................278
281
Barry Pangrle, Srikanth Jadcherla
11.1 Introduction..................................................................................281
11.2 Multiple voltage definitions and scenarios..................................283
11.3 Design examples..........................................................................290
11.4 Summary......................................................................................297
12. Winning the Power Struggle in an Uncertain Era 299
Murari Mani, Michael Orshansky
12.1 Introduction..................................................................................299
12.2 Process variability and its impact on power................................300
12.3 Parametric yield estimation .........................................................303
12.4 Optimization techniques for yield: an overview .........................305
12.5 Efficient statistical parametric yield maximization.....................308
12.6 Summary......................................................................................319
DESIGN EXAMPLES
13. Pushing ASIC Performance in a Power Envelope 323
Leon Stok, Ruchir Puri, Subhrajit Bhattacharya, John Cohn,
Dennis Sylvester, Ashish Srivastava, Sarvesh Kulkarni
13.1 Introduction..................................................................................324
13.2 Power-performance trade-off with multi-Vdd and multi-Vth.....324
13.3 Design issues in multi-Vdd ASICs..............................................332
13.4 Case study ....................................................................................344
13.5 Summary......................................................................................353
14. Low Power ARM 1136JF-S Design 357
George Kuo, Anand Iyer
14.1 Introduction..................................................................................357
14.2 Project objective ..........................................................................358
14.3 Key decisions and implemenations .............................................362
14.4 Results..........................................................................................377
14.5 Summary......................................................................................381

mscyc0909

After download, maybe you must add the ".rar" extension to file names due to extension missing. And then unpack them to get pdf file. Enjoy!

lgy747

Verification

sq143

学习 1# benemale

yaowengang771

低功耗应该和工艺关系也是密切相关的，不知书里提了没有
下来看看！