Whatever I do, I get simulation error. The Testbench can't instantiate modules inside it and can't connect to them so can't access to their internal structures. This is the reason I always get error in the waveform (Output signals are always Z or U).
Have you been able to solve this big problem?
It practically doesn't allow any project to be simulated.
I have the same simulation error in all versions of the patched Riviera.