iVerilog和VCS的仿真结果不一致？

mmo · 发表于 2023-8-13 09:54:27

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大家好，我最近在测试一个设计，发现iverilog和vcs仿真结果不一致的问题。
vcs的对 <= 的处理有问题，请大伙看看，这是一个真的问题吗？
举一个简单的例子，使用一个小设计adder：
Verilog code:

module top(input wire clk, input wire [27:0] io_in, output wire [27:0] io_out, io_oeb);
wire rst = io_in[0];
reg [15:0] ctr;
always @(posedge clk)
if (rst)
ctr <= 0;
else
ctr <= ctr + 1'b1;
assign io_out = {10'h123, ctr, rst, 1'b0}; // pass thru reset for debugging
assign io_oeb = 28'b1;
endmodule

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testbench in iverilog：

`timescale 1ps/1ps
module fab_tb;
wire [27:0] I_top;
wire [27:0] T_top;
reg [27:0] O_top = 0;
reg CLK = 1'b0;
wire [27:0] I_top_gold, oeb_gold, T_top_gold;
top dut_i (
.clk(CLK),
.io_out(I_top_gold),
.io_oeb(oeb_gold),
.io_in(O_top)
);
assign T_top_gold = ~oeb_gold;
always #50 CLK = (CLK === 1'b0);
integer i;
reg have_errors = 1'b0;
initial begin
repeat (100) @(posedge CLK);
O_top = 28'b1; // reset
repeat (5) @(posedge CLK);
O_top = 28'b0;
for (i = 0; i < 100; i = i + 1) begin
@(negedge CLK);
$display("cnt = 0x%X, f gold = 0x%X, gold = 0x%X", O_top, I_top_gold, T_top_gold);
end
if (have_errors)
$fatal;
else
$finish;
end
initial begin
$dumpfile("wave.vcd"); //
$dumpvars(0, fab_tb);
end
endmodule
module clk_buf(input A, output X);
assign X = A;
endmodule

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testbench in vcs:

module adder_tb;
wire [27:0] I_top;
wire [27:0] T_top;
reg [27:0] O_top = 0;
reg CLK = 1'b1;
wire [27:0] I_top_gold, oeb_gold, T_top_gold;
top dut_i (
.clk(CLK),
.io_out(I_top_gold),
.io_oeb(oeb_gold),
.io_in(O_top)
);
assign T_top_gold = ~oeb_gold;
always #50 CLK = (CLK === 1'b0);
//always begin
//#50
//CLK = ~CLK;
//end
//always #50 CLK = ~CLK ;
integer i;
reg have_errors = 1'b0;
initial begin
repeat (100) @(posedge CLK);
O_top = 28'b1; // reset
repeat (5) @(posedge CLK);
O_top = 28'b0;
//repeat (50) @(posedge CLK);
//$display("in_in = 0x%X, gold = 0x%X, gold = 0x%X", O_top, I_top_gold, T_top_gold);
for (i = 0; i < 100; i = i + 1) begin
@(negedge CLK);
$display("in_in = 0x%X, gold = 0x%X, gold = 0x%X", CLK, I_top_gold, T_top_gold);
end
if (have_errors)
$fatal;
else
$finish;
end
initial begin
$fsdbDumpfile("adder_tb.fsdb"); //
$fsdbDumpvars(0,adder_tb); //
//$fsdbDumpSVA();
//$fsdbDumpMDA();
//$vcdpluson;
//$vcdplusmemon;
end
endmodule
module clk_buf(input A, output X);
assign X = A;
endmodule