*ERROR* (AMS-1247): AMS UNL netlisting has failed.
Check Simulation->Output Log->Netlister Log for errors.
Correct your design and netlist again.
...unsuccessful.
以下是log文件：
WARNING (OSSHNL-143): Incremental netlisting is not possible since the global
map file
'/home/lsx/Research/TSMC_28nm_GP/simulation/lsx_202307_DAC_basic_TOP/ams/config/netlist/digital/ihnl/globalmap', could
not be opened in the read mode for IHNL
version number comparison. Therefore
re-netlisting the entire design.
INFO (VLOGNET-60): The stimulus name mapped table will not be printed in the
"/home/lsx/Research/TSMC_28nm_GP/simulation/lsx_202307_DAC_basic_TOP/ams/config/netlist/digital/testfixture.verilog" file. To print the stimulus name mapped
table, set
simVerilogPrintStimulusNameMappingTable = t either in CIW or the
.simrc file
before invoking Verilog netlister.
INFO (VLOGNET-62): Database internal net names will be printed for floating
instance ports. To prevent
them from being printed, set
simVerilogProcessNullPorts = t either in CIW or
the .simrc file.
INFO (VLOGNET-64): All cellviews in the design will be printed in the Netlist
Configuration list.
If you want to print only those cellviews that need to be
re-netlisted in the
list, set simVerilogIncrementalNetlistConfigList = t either
in CIW or the
.simrc file.
INFO (VLOGNET-68): The initial state of stimulus of all inout pins is set to
"z". To get inout
pins with initial state of "0", set
hnlVerilogIOInitStimulusStr = "0"
either in CIW or the .simrc file.
INFO (AMS-2150): Generating the 'changedVarsSummary' file in the 'netlist'
directory. This file prints the values of the netlister control variables, which
are different from their default values. To disable the file creation, type
'envSetVal("ams.netlisterOpts" "print_control_vars" 'boolean nil )' in the
'.cdsinit' file.
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发表于 2023-8-2 19:50:31
