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一本介绍vhdl的书,细节讲得很详细.
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您需要 登录 才可以下载或查看,没有账号?注册  This is the fourth version of the book and this version now not only provides
 VHDL language coverage but design methodology information as well. This
 version will guide the reader through the process of creating a VHDL
 design, simulating the design, synthesizing the design, placing and routing
 the design, using VITAL simulation to verify the final result, and a new
 technique called At-Speed debugging that provides extremely fast design
 verification. The design example in this version has been updated to reflect
 the new focus on the design methodology.
 This book was written to help hardware design engineers learn how to
 write good VHDL design descriptions. The goal is to provide enough VHDL
 and design methodology information to enable a designer to quickly write
 good VHDL designs and be able to verify the results. It will also attempt
 to bring the designer with little or no knowledge of VHDL, to the level of
 writing complex VHDL descriptions. It is not intended to show every possible
 construct of VHDL in every possible use, but rather to show the designer
 how to write concise, efficient, and correct VHDL descriptions of
 hardware designs.
 
 [ 本帖最后由 simonccn 于 2008-1-28 21:36 编辑 ]
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