为什么这种运放结构可以增大基准的PSR

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ol0930 发表于 2023-6-25 18:12
因为最后一级的负载是二极管连接的pmos。

当电源VDDA出现ripple的时候，M9的D端通过受到的电源ripple影响 ...

谢谢大佬的解答，豁然开朗

aznsj

1. those say gain helps on PSR is only valid for DC psrr. but usually PSR worst at middle frequency.
2. those say the output is tied to gate of NMOS , is not correct, because at middle or high frequency the opamp gain is not high
3. the design is not the full picture, it should has the loading cell, and PSR is worse , since the impedance looked up is 1/gm, the load impedance is usually higher than 1/gm.  

pls fee free to correct me.

icdane

do some simulation.
tricky to say that the diode connected PMOS following the supply noise here benefits the PSRR. the amp itself has the 2nd stage, which also worsens the PSRR (for the 1st stage, as long as it balanced, the noise then is CM noise, will be cancelled out).
at relatively high freq, 2nd stage introduced noise is gm8/gm9*gm7/gm6, which is about -1 --> BG PMOS current source then still sees the supply noises.