求求大佬们帮忙看看这个DC问题怎么解决，已经dc_shell-t了

藏在风的过往里

Compiling source file ../source/CRC5.v
Error:  ../source/CRC5.v:36: Variable 'next_crc' is the target of both blocking and nonblocking assignments in the same always block. (VER-134)
*** Presto compilation terminated with 1 errors. ***
Loading db file '/home/demo/eda_lib/1.0v/scc55nll_hd_lvt_ss_v0p9_125c_ccs.db'
Information: Using CCS timing libraries. (TIM-024)
Warning: Detected use of obsolete/unsupported feature.  The following
        will not be available in a future release of the application:
        elaborate -update. Use plain elaborate instead (CMD-100)
Loading db file '/tools/synopsys/syn_vK-2015.06/libraries/syn/gtech.db'
Loading db file '/tools/synopsys/syn_vK-2015.06/libraries/syn/standard.sldb'
  Loading link library 'scc55nll_hd_lvt_ss_v0p9_125c_ccs'
  Loading link library 'gtech'
Error: Can't find the architecture 'CRC5(verilog)' in the library 'WORK'
Running PRESTO hdlC
Compiling source file ../source/CRC6.v
Error:  ../source/CRC6.v:41: Variable 'next_crc' is the target of both blocking and nonblocking assignments in the same always block. (VER-134)
*** Presto compilation terminated with 1 errors. ***
Warning: Detected use of obsolete/unsupported feature.  The following
        will not be available in a future release of the application:
        elaborate -update. Use plain elaborate instead (CMD-100)
Error: Can't find the architecture 'CRC6(verilog)' in the library 'WORK'
Running PRESTO HDLC
Compiling source file ../source/TOP.v
Error:  ../source/TOP.v:1: Port 'crc_reg1' not declared as 'input', 'output' or 'inout'. (VER-120)
Error:  ../source/TOP.v:13: Symbol crc_reg not included in portlist (VER-149)
*** Presto compilation terminated with 2 errors. ***
Warning: Detected use of obsolete/unsupported feature.  The following
        will not be available in a future release of the application:
        elaborate -update. Use plain elaborate instead (CMD-100)
Error: Can't find the architecture 'TOP(verilog)' in the library 'WORK'
Error: Current design is not defined. (UID-4)
Error: Can't find design 'TOP'. (UID-109)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)
# Define system clock period
set clk_period 6.4
6.4
#set SysClk_period 3
#Create real clock if clock port is found
if {[sizeof_collection [get_ports clk]] > 0} {
   set clk_name clk
   create_clock -period $clk_period $clk_name
}
Error: Current design is not defined. (UID-4)
Error: Can't find port 'clk'. (UID-109)
# for I/O ports
#set_load [expr [load_of scc55nll_hd_rvt_tt_v1p2_25c_basic/BUFHDV0/I] * 20] [all_outputs]
# If real clock, set infinite drive strength
if {[sizeof_collection [get_ports clk]] > 0} {
   set_drive 0 [get_ports clk]
}
Error: Current design is not defined. (UID-4)
Error: Can't find port 'clk'. (UID-109)
set_dont_touch_network [get_clock clk]
Error: Current design is not defined. (UID-4)
Error: Can't find clock 'clk'. (UID-109)
Error: Value for list '<object_list>' must have 1 elements. (CMD-036)
0
#create_clock -name SysClk -period 3 [get_pins pll/CLK_OUT]
# Apply default timing constraints for modules
set_input_delay 3.2  -clock $clk_name  [remove_from_collection [all_inputs] [get_ports  "clk"]]
Error: can't read "clk_name": no such variable
        Use error_info for more info. (CMD-013)
set_output_delay 3.2 -clock $clk_name   [all_outputs]
Error: can't read "clk_name": no such variable
        Use error_info for more info. (CMD-013)
set_ideal_network [get_ports "clk"]
Error: Current design is not defined. (UID-4)
Error: Can't find port 'clk'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
0
set_ideal_network [get_ports "rst"]
Error: Current design is not defined. (UID-4)
Error: Can't find port 'rst'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
0
set_dont_touch_network [get_ports "clk"]
Error: Current design is not defined. (UID-4)
Error: Can't find port 'clk'. (UID-109)
Error: Value for list '<object_list>' must have 1 elements. (CMD-036)
0
set_dont_touch_network [get_ports "rst"]
Error: Current design is not defined. (UID-4)
Error: Can't find port 'rst'. (UID-109)
Error: Value for list '<object_list>' must have 1 elements. (CMD-036)
0
# Set operating conditions
#foreach_in_collection clk_name1 [all_clocks]{
#foreach_in_collectin clk_name2  [remove_from_collection [all_clocks]] [get_clock $clk_name1]]{
#set_false_path -from [get_clocks $clk_name1] -to [get_clocks $clk_name2]
#}
# }
#set_operating_conditions tt_v1p2_25c
# Turn on auto wire load selection
# (library must support this feature)
set auto_wire_load_selection true
true
#set dont use
#set dont_use_list "*G_A9TR40 *_A9TL* *_XOP* *ISO* *LVL* D* GPG* HEAD* FOOT* ITE* D* DLY* ESD* END* OAI222* OR6_* RF* "
#foreach cell $dont_use_list {
# if { [sizeof_collection [ get_lib_cells -quiet */$cell]] != "0"} {
# set_dont_use [ get_lib_cells */$cell ]
Error: Current design is not defined. (UID-4)
Error: No files or designs were specified. (UID-22)
Error: Current design is not defined. (UID-4)
Error: Current design is not defined. (UID-4)

hzhou

RTL代码错误较多，先修改CRC5.v、CRC6.v、TOP.v中的明显错误，再编译看；

藏在风的过往里

Variable 'next_crc' is the target of both blocking and nonblocking assignments in the same always block.   大佬，这个问题怎么解决啊，试了好几次了

藏在风的过往里

hzhou 发表于 2023-6-11 12:20
RTL代码错误较多，先修改CRC5.v、CRC6.v、TOP.v中的明显错误，再编译看；

大佬，DC问题已经解决了。但是在跑FM时又出现了这样的错误
Error: Unsuppressed RTL interpretation message(s) :
FMR_ELAB-059
were produced during link. (FM-262)
Error: Failed to set top design to 'r:/WORK/CRC_TOP' (FM-156)

voiluce

Error: Unsuppressed RTL interpretation message(s) :
===
看看前面读RTL的错误。。。