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报错如下:PO.R.19 { @ Floating gate is prohibited if the effective source/drain are not connected together. Floating gate in the DRC is as follows: (1) GATE without Poly CO (2) GATE with Poly CO but not connected to MOS OD, STRAP or PAD. (3) It is not a floating gate if the GATE is connected to OD by butted CO in SRAM bit cell. The effective source/drain in DRC is as follows: (1)Source/drain is connected to different {MOSOD NOT PO}, STRAP, Gate, or PAD. This rule is only checked on the whole chip, not on the IP level
(Float_GATE_check INTERACT NSDu > 1 BY NET) NOT INSIDE SRAM_WAIVE_N28
(Float_GATE_check INTERACT PSDu > 1 BY NET) NOT INSIDE SRAM_WAIVE_N28
}
输入栅极都连接焊盘了还报错
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