Design of Charge Pump in Low-Voltage CMOS Processes(Ker)

buildgates

gooooood

vbjkkk

tracy_smile

楼主很细心周到哦，abstract and conclusion都有了。值得大家学习！

alex_bai

smilelangjun

thanks
good！

sjxu007

pump good

sjxu007

xieeeeeeeeeeeeeeeeeeeeeeeeeeeeee

sprun

这本怎么样啊？

guillermo

Abstract—Anew charge pump circuit with consideration of gateoxide
reliability is designed with two pumping branches in this
paper. The charge transfer switches in the new proposed circuit
can be completely turned on and turned off, so its pumping efficiency
is higher than that of the traditional designs. Moreover,
the maximum gate-source and gate-drain voltages of all devices in
the proposed charge pump circuit do not exceed the normal operating
power supply voltage (VDD). Two test chips have been implemented
in a 0.35- m 3.3-V CMOS process to verify the new proposed
charge pump circuit. The measured output voltage of the
new proposed four-stage charge pump circuit with each pumping
capacitor of 2 pF to drive the capacitive output load is around 8.8 V
under 3.3-V power supply (VDD = 3 3 V), which is limited by
the junction breakdown voltage of the parasitic pn-junction in the
given process. The new proposed circuit is suitable for applications
in low-voltage CMOS processes because of its high pumping efficiency
and no overstress across the gate oxide of devices.
Index Terms—Body effect, charge pump circuit, gate-oxide reliability,
high-voltage generator, low voltage.

guillermo

Abstract—Anew charge pump circuit with consideration of gateoxide
reliability is designed with two pumping branches in this
paper. The charge transfer switches in the new proposed circuit
can be completely turned on and turned off, so its pumping efficiency
is higher than that of the traditional designs. Moreover,
the maximum gate-source and gate-drain voltages of all devices in
the proposed charge pump circuit do not exceed the normal operating
power supply voltage (VDD). Two test chips have been implemented
in a 0.35- m 3.3-V CMOS process to verify the new proposed
charge pump circuit. The measured output voltage of the
new proposed four-stage charge pump circuit with each pumping
capacitor of 2 pF to drive the capacitive output load is around 8.8 V
under 3.3-V power supply (VDD = 3 3 V), which is limited by
the junction breakdown voltage of the parasitic pn-junction in the
given process. The new proposed circuit is suitable for applications
in low-voltage CMOS processes because of its high pumping efficiency
and no overstress across the gate oxide of devices.
Index Terms—Body effect, charge pump circuit, gate-oxide reliability,
high-voltage generator, low voltage.