Design of Charge Pump in Low-Voltage CMOS Processes(Ker)

semico_ljj

Design of Charge Pump Circuit With
Consideration of Gate-Oxide Reliability
in Low-Voltage CMOS Processes


Ming-Dou Ker, Senior Member, IEEE, Shih-Lun Chen, Student Member, IEEE, and Chia-Shen Tsai

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 5, MAY 2006

semico_ljj

Abstract—Anew charge pump circuit with consideration of gateoxide
reliability is designed with two pumping branches in this
paper. The charge transfer switches in the new proposed circuit
can be completely turned on and turned off, so its pumping efficiency
is higher than that of the traditional designs. Moreover,
the maximum gate-source and gate-drain voltages of all devices in
the proposed charge pump circuit do not exceed the normal operating
power supply voltage (VDD). Two test chips have been implemented
in a 0.35- m 3.3-V CMOS process to verify the new proposed
charge pump circuit. The measured output voltage of the
new proposed four-stage charge pump circuit with each pumping
capacitor of 2 pF to drive the capacitive output load is around 8.8 V
under 3.3-V power supply (VDD = 3 3 V), which is limited by
the junction breakdown voltage of the parasitic pn-junction in the
given process. The new proposed circuit is suitable for applications
in low-voltage CMOS processes because of its high pumping efficiency
and no overstress across the gate oxide of devices.
Index Terms—Body effect, charge pump circuit, gate-oxide reliability,
high-voltage generator, low voltage.

semico_ljj

CONCLUSION
A new charge pump circuit realized with only low-voltage
devices without suffering the gate-oxide reliability issue has
been presented. Because the charge transfer switches of the new
proposed charge pump circuit can be fully turned on and turned
off, as well as the output stage does not have the threshold
drop problem, its pumping efficiency is higher than that of the
prior designs. The gate-drain and the gate-source voltages of
all devices in the proposed charge pump circuit do not exceed
VDD, so the proposed charge pump circuit does not suffer
the gate-oxide reliability problem. Two test chips have been
implemented in a 0.35- m 3.3-V CMOS process. The experimental
results have shown that the new proposed four-stage
charge pump circuit with each pumping capacitor of 2 pF to
drive the capacitive load is around 8.8 V under 3.3-V power
supply VDD V . With the higher pumping gain and no
overstress across the gate oxide, the new proposed charge pump
circuit is more suitable for applications in low-voltage CMOS
integrated circuits to generate the specified high voltage.

fanjx

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jianchongzhou

是IEEE的文章

kaorukaoru

thanks~~~~~

jcchan

很好的資料，感謝大大無私的分享。

abcd1234x

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leonwenli

两个清华去伯克利的学生作的文章,顶!

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