Innovus place_design后没反应

liki799

初学Innovus 跑到place_design这步后应该layout会出来器件和部分布线，可以实际上什么也没有变化。看提示好像都成功了。请大神指点。
最后出来这个Tdgp not successfully inited but do clear! 是什么意思？


To increase the message display limit, refer to the product command reference manual.
Total number of fetched objects 6164
AAE_INFO: Total number of nets for which stage creation was skipped for all views 0
End delay calculation. (MEM=1551.41 CPU=0:00:00.7 REAL=0:00:00.0)
End delay calculation (fullDC). (MEM=1551.41 CPU=0:00:00.9 REAL=0:00:00.0)
**INFO: Disable pre-place timing setting for timing analysis
Set Using Default Delay Limit as 1000.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
**INFO: Pre-place timing setting for timing analysis already disabled
Deleted 0 physical inst  (cell - / prefix -).
INFO: #ExclusiveGroups=0
INFO: There are no Exclusive Groups.
*** Starting "NanoPlace(TM) placement v#15 (mem=1541.9M)" ...
*** Build Buffered Sizing Timing Model
(cpu=0:00:02.1 mem=1541.9M) ***
*** Build Virtual Sizing Timing Model
(cpu=0:00:02.2 mem=1541.9M) ***
No user-set net weight.
Net fanout histogram:
2                : 3334 (56.3%) nets
3                : 1090 (18.4%) nets
4     -        14        : 1346 (22.7%) nets
15    -        39        : 141 (2.4%) nets
40    -        79        : 4 (0.1%) nets
80    -        159        : 1 (0.0%) nets
160   -        319        : 0 (0.0%) nets
320   -        639        : 2 (0.0%) nets
640   -        1279        : 0 (0.0%) nets
1280  -        2559        : 0 (0.0%) nets
2560  -        5119        : 0 (0.0%) nets
5120+                : 0 (0.0%) nets
Options: timingDriven clkGateAware ignoreScan pinGuide congEffort=auto gpeffort=medium
*** Scan Trace Summary (runtime: cpu: 0:00:00.0 , real: 0:00:00.0):
Successfully traced 2 scan chains (total 540 scan bits).
Start applying DEF ordered sections ...
Successfully applied all DEF ordered sections.
*** Scan Sanity Check Summary:
*** 2 scan chains passed sanity check.
#std cell=5551 (0 fixed + 5551 movable) #buf cell=0 #inv cell=316 #block=4 (0 floating + 4 preplaced)
#ioInst=499 #net=5903 #term=21759 #term/net=3.69, #fixedIo=499, #floatIo=0, #fixedPin=57, #floatPin=0
stdCell: 5551 single + 0 double + 0 multi
Total standard cell length = 25.8324 (mm), area = 0.1302 (mm^2)
Average module density = 0.515.
Density for the design = 0.515.
       = stdcell_area 39140 sites (130195 um^2) / alloc_area 76039 sites (252937 um^2).
Pin Density = 0.09932.
            = total # of pins 21759 / total area 219072.
=== lastAutoLevel = 9
Clock gating cells determined by native netlist tracing.
Iteration  1: Total net bbox = 1.414e+05 (8.15e+04 5.99e+04)
              Est.  stn bbox = 1.663e+05 (9.52e+04 7.11e+04)
              cpu = 0:00:00.1 real = 0:00:01.0 mem = 1520.9M
Iteration  2: Total net bbox = 1.414e+05 (8.15e+04 5.99e+04)
              Est.  stn bbox = 1.663e+05 (9.52e+04 7.11e+04)
              cpu = 0:00:00.0 real = 0:00:00.0 mem = 1520.9M
Iteration  3: Total net bbox = 1.820e+05 (9.42e+04 8.78e+04)
              Est.  stn bbox = 2.319e+05 (1.21e+05 1.11e+05)
              cpu = 0:00:00.5 real = 0:00:00.0 mem = 1529.0M
Active setup views:
    dtmf_view_setup
Iteration  4: Total net bbox = 2.081e+05 (9.56e+04 1.12e+05)
              Est.  stn bbox = 2.657e+05 (1.23e+05 1.43e+05)
              cpu = 0:00:00.8 real = 0:00:01.0 mem = 1529.0M
Iteration  5: Total net bbox = 2.408e+05 (1.08e+05 1.33e+05)
              Est.  stn bbox = 3.050e+05 (1.38e+05 1.67e+05)
              cpu = 0:00:01.0 real = 0:00:01.0 mem = 1529.0M
Iteration  6: Total net bbox = 2.624e+05 (1.30e+05 1.33e+05)
              Est.  stn bbox = 3.320e+05 (1.65e+05 1.67e+05)
              cpu = 0:00:01.5 real = 0:00:01.0 mem = 1529.0M

Iteration  7: Total net bbox = 2.664e+05 (1.32e+05 1.34e+05)
              Est.  stn bbox = 3.360e+05 (1.67e+05 1.69e+05)
              cpu = 0:00:00.1 real = 0:00:01.0 mem = 1529.0M
Iteration  8: Total net bbox = 2.664e+05 (1.32e+05 1.34e+05)
              Est.  stn bbox = 3.360e+05 (1.67e+05 1.69e+05)
              cpu = 0:00:01.2 real = 0:00:01.0 mem = 1542.6M
Iteration  9: Total net bbox = 2.774e+05 (1.39e+05 1.39e+05)
              Est.  stn bbox = 3.503e+05 (1.76e+05 1.75e+05)
              cpu = 0:00:02.5 real = 0:00:02.0 mem = 1560.1M
Iteration 10: Total net bbox = 2.774e+05 (1.39e+05 1.39e+05)
              Est.  stn bbox = 3.503e+05 (1.76e+05 1.75e+05)
              cpu = 0:00:01.2 real = 0:00:01.0 mem = 1560.1M
Iteration 11: Total net bbox = 2.801e+05 (1.40e+05 1.40e+05)
              Est.  stn bbox = 3.531e+05 (1.77e+05 1.76e+05)
              cpu = 0:00:02.2 real = 0:00:03.0 mem = 1560.1M
Iteration 12: Total net bbox = 2.801e+05 (1.40e+05 1.40e+05)
              Est.  stn bbox = 3.531e+05 (1.77e+05 1.76e+05)
              cpu = 0:00:01.3 real = 0:00:01.0 mem = 1560.1M
Iteration 13: Total net bbox = 2.904e+05 (1.45e+05 1.45e+05)
              Est.  stn bbox = 3.622e+05 (1.82e+05 1.80e+05)
              cpu = 0:00:05.7 real = 0:00:05.0 mem = 1564.1M
Iteration 14: Total net bbox = 2.904e+05 (1.45e+05 1.45e+05)
              Est.  stn bbox = 3.622e+05 (1.82e+05 1.80e+05)
              cpu = 0:00:00.0 real = 0:00:00.0 mem = 1564.1M
Iteration 15: Total net bbox = 2.904e+05 (1.45e+05 1.45e+05)
              Est.  stn bbox = 3.622e+05 (1.82e+05 1.80e+05)
              cpu = 0:00:00.0 real = 0:00:00.0 mem = 1564.1M
*** cost = 2.904e+05 (1.45e+05 1.45e+05) (cpu for global=0:00:18.1) real=0:00:18.0***
Info: 0 clock gating cells identified, 0 (on average) moved 0/7
Solver runtime cpu: 0:00:13.5 real: 0:00:13.4
Core Placement runtime cpu: 0:00:14.3 real: 0:00:14.0
*** Scan Trace Summary (runtime: cpu: 0:00:00.0 , real: 0:00:00.0):
Successfully traced 2 scan chains (total 540 scan bits).
*** Scan Skip Mode Summary:
*** Scan Trace Summary (runtime: cpu: 0:00:00.0 , real: 0:00:00.0):
Successfully traced 2 scan chains (total 540 scan bits).
Start applying DEF ordered sections ...
Successfully applied all DEF ordered sections.
*** Scan Sanity Check Summary:
*** 2 scan chains passed sanity check.
*** Summary: Scan Reorder within scan chain
Initial total scan wire length:    19795.720 (floating:    19275.503)
Final   total scan wire length:    13417.697 (floating:    12897.480)
Improvement:     6378.023   percent 32.22 (floating improvement:     6378.023   percent 33.09)
Initial scan reorder max long connection: not available for -stitchChainsAfterFreeMerging
Final   scan reorder max long connection:      528.808
Total net length = 2.904e+05 (1.454e+05 1.450e+05) (ext = 0.000e+00)
*** End of ScanReorder (cpu=0:00:00.0, real=0:00:00.0, mem=1756.1M) ***
*** Starting refinePlace (5:45:18 mem=1756.1M) ***
Total net bbox length = 2.959e+05 (1.484e+05 1.474e+05) (ext = 2.773e+04)
Move report: Detail placement moves 5551 insts, mean move: 3.62 um, max move: 33.45 um
        Max move on inst (DTMF_INST/TDSP_CORE_INST/MPY_32_INST/M16X16_INST/i_249): (407.24, 980.53) --> (393.36, 960.96)
        Runtime: CPU: 0:00:00.3 REAL: 0:00:00.0 MEM: 1756.1MB
Summary Report:
Instances move: 5551 (out of 5551 movable)
Instances flipped: 0
Mean displacement: 3.62 um
Max displacement: 33.45 um (Instance: DTMF_INST/TDSP_CORE_INST/MPY_32_INST/M16X16_INST/i_249) (407.237, 980.529) -> (393.36, 960.96)
        Length: 4 sites, height: 1 rows, site name: tsm3site, cell type: AND2X1
Total net bbox length = 2.894e+05 (1.409e+05 1.485e+05) (ext = 2.776e+04)
Runtime: CPU: 0:00:00.3 REAL: 0:00:00.0 MEM: 1756.1MB
*** Finished refinePlace (5:45:18 mem=1756.1M) ***
*** End of Placement (cpu=0:00:21.2, real=0:00:21.0, mem=1756.1M) ***
default core: bins with density > 0.750 = 51.96 % ( 159 / 306 )
Density distribution unevenness ratio = 17.765%
*** Free Virtual Timing Model ...(mem=1756.1M)
**INFO: Enable pre-place timing setting for timing analysis
Set Using Default Delay Limit as 101.
**WARN: (IMPDC-1629):        The default delay limit was set to 101. This is less than the default of 1000 and may result in inaccurate delay calculation for nets with a fanout higher than the setting.  If needed, the default delay limit may be adjusted by running the command 'set delaycal_use_default_delay_limit'.
Set Default Net Delay as 0 ps.
Set Default Net Load as 0 pF.
**INFO: Analyzing IO path groups for slack adjustment
Effort level <high> specified for reg2reg_tmp.321891 path_group
#################################################################################
# Design Stage: PreRoute
# Design Name: DTMF_CHIP
# Design Mode: 180nm
# Analysis Mode: MMMC Non-OCV
# Parasitics Mode: No SPEF/RCDB
# Signoff Settings: SI Off
#################################################################################
Calculate delays in BcWc mode...
Start delay calculation (fullDC) (1 T). (MEM=1744.61)
Total number of fetched objects 6164
AAE_INFO: Total number of nets for which stage creation was skipped for all views 0
End delay calculation. (MEM=1724.11 CPU=0:00:00.6 REAL=0:00:01.0)
End delay calculation (fullDC). (MEM=1724.11 CPU=0:00:00.8 REAL=0:00:01.0)
**INFO: Disable pre-place timing setting for timing analysis
Set Using Default Delay Limit as 1000.
Set Default Net Delay as 1000 ps.
Set Default Net Load as 0.5 pF.
Info: Disable timing driven in postCTS congRepair.

Starting congRepair ...
[NR-eGR] Num Prerouted Nets = 0  Num Prerouted Wires = 0
[NR-eGR] Read numTotalNets=5918  numIgnoredNets=0
[NR-eGR] There are 6 clock nets ( 0 with NDR ).
[NR-eGR] ============ Routing rule table ============
[NR-eGR] Rule id: 0  Nets: 5861
[NR-eGR] ========================================
[NR-eGR]
[NR-eGR] Layer group 1: route 5861 net(s) in layer range [2, 6]
[NR-eGR] Early Global Route overflow of layer group 1: 0.00% H + 0.00% V. EstWL: 3.346006e+05um
[NR-eGR] Overflow after Early Global Route (GR compatible) 0.04% H + 0.00% V
[NR-eGR] Overflow after Early Global Route 0.05% H + 0.00% V
Early Global Route congestion estimation runtime: 0.18 seconds, mem = 1722.6M
Local HotSpot Analysis: normalized max congestion hotspot area = 0.00, normalized total congestion hotspot area = 0.00 (area is in unit of 4 std-cell row bins)
Skipped repairing congestion.
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Metal1  (1F) length: 0.000000e+00um, number of vias: 22033
[NR-eGR] Metal2  (2V) length: 1.091793e+05um, number of vias: 33089
[NR-eGR] Metal3  (3H) length: 1.387318e+05um, number of vias: 2617
[NR-eGR] Metal4  (4V) length: 4.688421e+04um, number of vias: 658
[NR-eGR] Metal5  (5H) length: 2.976318e+04um, number of vias: 254
[NR-eGR] Metal6  (6V) length: 2.195592e+04um, number of vias: 0
[NR-eGR] Total length: 3.465144e+05um, number of vias: 58651
[NR-eGR] --------------------------------------------------------------------------
[NR-eGR] Total eGR-routed clock nets wire length: 8.123775e+03um
[NR-eGR] --------------------------------------------------------------------------
Early Global Route wiring runtime: 0.31 seconds, mem = 1509.6M
Tdgp not successfully inited but do clear! skip clearing
End of congRepair (cpu=0:00:00.5, real=0:00:01.0)
*** Finishing placeDesign default flow ***
***** Total cpu  0:0:25
***** Total real time  0:0:25
**placeDesign ... cpu = 0: 0:25, real = 0: 0:25, mem = 1509.6M **
Tdgp not successfully inited but do clear! skip clearing

*** Summary of all messages that are not suppressed in this session:
Severity  ID               Count  Summary                                 
WARNING   IMPMSMV-1810      1324  Net %s, driver %s (cell %s) voltage %g d...
WARNING   IMPDC-1629           2  The default delay limit was set to %d. T...
*** Message Summary: 1326 warning(s), 0 error(s)

liki799

补充：该问题已解决，是视图问题，右上角有视图切换图标，切换为physics view就可以看到器件了。

cqu_luj

请问明白了这个tdgp到底是什么意思吗

Quinn714

DTMF_CHIP的lab吗